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Thursday, February 25, 2010

Arrays and Records in VHDL

In many situations you may have to use a 2-D array in your design.A 2-D array can be declared in two ways in VHDL.I will show examples:

1)Using the keyword "array".  
--first example
type array_type1 is array (0 to 3) of integer; --first define the type of array.
signal array_name1 : array_type1;  --array_name1 is a 4 element array of integers.
--second example
 --first define the type of array.
type array_type2 is array (0 to 3) of std_logic_vector(11 downto 0); 
signal array_name2 : array_type2;   --array_name2 is a 4 element array of 12-bit vectors.

2)Array of different kind of elements.
        Using array ,you can easily create an  array of similar types.But what will you do if you want an array of different type of elements,like the structures in C programming.For handling such data types there is another keyword available in VHDL-"record".
--third example
type record_name is
     a : std_logic_vector(11 downto 0);
     b: std_logic_vector(2 downto 0);
     c : std_logic;
  end record;
type array_type3 is array (0 to 3) of record_name; --first define the type of array.
signal actual_name : array_type3;
     After going through the above examples you must have got an idea about array and record declarations.Now we will see how to access them from the program.
 If the array name is "var_name" then the individual elements can be accessed by the following notation : var_name(0),var_name(1) etc....

--an example
signal test1 : std_logic_vector(11 downto 0);
test1 <= array_name2(0);
signal test2 : integer;
test2 <= array_name1(2);
--accessing the record.
a1 : std_logic_vector(11 downto 0);
b1: std_logic_vector(2 downto 0);
c1 : std_logic;
a1 <= actual_name(1).a;
b1 <= actual_name(1).b;
c1 <= actual_name(1).c;
actual_name(2).a <= "100011100011";
actual_name(1) <= (a =>  "100011100011", b => "101", c => '1');
actual_name(0) <= ("100011100011","101",'1');

Sometimes you may need to initialize a large array to zeros.If the array is very large then it is tedious to initialize it using the above methods.A keyword called "others" is used in such cases.

--an example illustrating the usage of "others".
signal test4 : std_logic_vector(127downto 0) :=  (others =>'0');
--test5 ="00000010";
signal test5 : std_logic_vector(7 downto 0) := (1 =>'1', (others =>'0') );
--initializing a 4 element array of 12 bit elements to zero.
array_name2 <= (others=> (others=>'0'));

--A 2-d array declaration
type array_type2 is array (0 to 3) of std_logic_vector(11 downto 0);
type array_type4 is array (0 to 2) of array_type2;
signal array_name4 : array_type4;  --array_name4 is a 3*4 two dimensional array.
--initialization to zeros.

Hope this small tutorial really helped you.
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