VHDL coding tips and tricks: How to test your design without writing a seperate test bench program?
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Monday, March 29, 2010

How to test your design without writing a seperate test bench program?

      Once you have finished writing code for your design,you need to test whether it is working or not.Usually this is done by writing a testbench code.Your module to be tested ( known as UUT - Unit Under Test) is declared as a component in this testbench code and inputs are set with required timings.
      So everything is fine.You just write a testbench code for your design and simulate.Verify the results.Now what is this article about?One disadvantage of the above method is that you need to write lot of unnecessary code in the form of component initiation,signal declarations etc., for testing your design.Testbench code also needs a new file.For big modules this is fine.But what if you are just playing around with VHDL and needs to test arbitrary designs with different input and output formats.Then writing different testbench files for each of them will definitly waste your time.
      So for small codes,you can put your testbench code in your main design file.I have explained it with the help of "counter" example given here.The code is divided by comment lines so that you can get a good overview of what I have done.

-------------------------Library declarations are not changed
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--------------------------------------------

entity test is
------------------------Port declaration Taken out from original code.
--port (clk : in std_logic;
--      count : out std_logic_vector(3 downto 0);
--     reset :in std_logic
--     );
--------------------------------------------
end test;

architecture Behavioral of test is
signal c : std_logic_vector(3 downto 0) :=(others => '0');
-------------------------new signals are added here
   constant clk_period : time := 1 ns;     --time period of clk.
        --declare the inputs and outputs of your design as signals.
   signal clk : std_logic := '0';
   signal reset : std_logic := '0';
   signal count : std_logic_vector(3 downto 0);
---------------------------------------------------    
begin

----------------------------process for generating clock.
   clk_process :process
   begin
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
   end process;
--------------------------------------End of clock generation

----------------------Simulation process(Set inputs here)
  stim_proc: process
   begin      
        wait for 7 ns;
        reset <='1';
        wait for 3 ns;
        reset <='0';
        wait for 17 ns;
        reset <= '1';
        wait for 1 ns;
        reset <= '0';
        wait;
  end process;
--------------------------End of simulation process

-------------------------Here comes your original code.  
count <= c;

process(clk,reset)
begin
if(clk'event and clk='1') then
if(c = "1111") then
c <="0000";
end if;
c <= c+'1';
end if;
if(reset='1') then
c <=(others => '0');
end if;
end process;

end Behavioral;

    The changes I have made are :
1) Your entity doesnt have any input or output declarations.
2)All your original inputs and outputs are declared as signals in the code.
3)If your design is clock driven then declare a constant for period of clock as follows:
        constant clk_period : time := 1 ns;     --time period of clk= 1ns.
4)Write the indicated code for clock generation process.
5)Define another process for applying the simulation inputs with proper timing.The contents of this process depends upon the logic you want to test and the test values.
6)Finally your original code is pasted as shown.
    

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