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Monday, March 8, 2010

Is 'case' statement more efficient than 'if..elsif..else' ?

   Is 'case' statement more efficient than 'if..elsif..else' statement in VHDL.The answer is "NO".Or you can say both the statements are equally efficient when it comes to hardware implementation.
Let me show this with  the help of an example.

--This program uses if..elsif..else statements for implementing the logic.
--You need not go through the logic,as it is just given for an example sake..
if(clk'event and clk='1') then
count <=count+'1';
end if;
if(count ="0000") then
output1 <= "0010";
elsif(count ="0001") then
output1 <= "0011";
elsif(count ="0010") then
output1 <= "0101";
elsif(count ="0011") then
output1 <= "0110";
end if;
end process;

After implementing the module and synthesizing it,I got the following RTL schematic.Some synthesization details are also given below.

   Minimum period: 1.118ns (Maximum Frequency: 894.374MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 3.488ns

--Now the above logic is written using the 'case' statement.
--The functionality is same for both the codes.
if(clk'event and clk='1') then
count <=count+'1';
end if;
case  count  is
          when  "0000" =>  output1 <= "0010";
          when  "0001"  => output1 <= "0011";
          when  "0010" => output1  <= "0101";
          when  "0011" => output1 <= "0110";              
          when others =>  output1 <= "0111";
end case;
end process;

I synthesized this code and got the exact results.Even the RTL schematic was exactly same for both of the programs.

Note :-  This shows that 'case' and 'if...elsif...else' statements are both equally efficient.But if you want to write a clear code,then you better use 'case'.'case' is very useful when the output depends upon a large number of conditions.But if the number of conditions are very small(2 or 3) then you can use 'if..elseif..else'.


  1. thats not the case of interest. the place the verilog coders care is the one-hot case. eg:
    0001, 0010, 0100, 1000. VHDL offers a way of hinting that these cases are mutually exclusive -- enumerated types.

    verilog has some synthesis switches to do a similar thing, but due to the ability to to have overlapping cases, it can end badly.

  2. Don't you use IF/elseIf to target the critical path?
    In your example, the path for if count="0000" would be less compared to if count="0011"

  3. I'd listen that it can depend strongly of the Hardware and their manofacturer... but i don't know if this is true or not. For example, some manofacture can recomends uses if and other uses the case...


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