Random Number Generator in VHDL

     In some designs you may need a Random Number Generator for generating random numbers.In C and other high level languages you have library functions for this kind of functions.In VHDL this is achieved by designing a pseudo random sequence generator (PRSG) of suitable length. The PRSG I have coded, will look like this:

 
     The sequence generated by PRSG is not theoretically  random,but for most practical applications the sequence can be considered as random.Because the period of the sequence is (2^n - 1).Where n is the number of shift registers used in the design.For 32 bit design the period is 4294967295.This is large enough for most of the practical applications.

   The module is written in a generic way.That means the value of 'n' can be specified at the time of compilation.
Below is the code:
 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity random is
    generic ( width : integer :=  32 );
port (
      clk : in std_logic;
      random_num : out std_logic_vector (width-1 downto 0)   --output vector           
    );
end random;

architecture Behavioral of random is
begin
process(clk)
variable rand_temp : std_logic_vector(width-1 downto 0):=(width-1 => '1',others => '0');
variable temp : std_logic := '0';
begin
if(rising_edge(clk)) then
temp := rand_temp(width-1) xor rand_temp(width-2);
rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0);
rand_temp(0) := temp;
end if;
random_num <= rand_temp;
end process;

     The test bench for the code is given below:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS
   --Input and Output definitions.
   signal clk : std_logic := '0';
   signal random_num : std_logic_vector(3 downto 0);
   -- Clock period definitions
   constant clk_period : time := 1 ns;
BEGIN
        -- Instantiate the Unit Under Test (UUT)
   uut: entity work.random generic map (width => 4) PORT MAP (
          clk => clk,
          random_num => random_num
        );
   -- Clock process definitions
   clk_process :process
   begin
                clk <= '0';
                wait for clk_period/2;
                clk <= '1';
                wait for clk_period/2;
   end process;

END;

The simulated waveform is shown below.

The code is synthesizable.The RTL schematic of the design is given below:

   The above test bench program passes the value '4' to the main code in  a generic manner so  that the output generated by the code is 4 bit in size.For more information about usage of Generics in VHDL,you can see this article.You can change the size of the output as you want by editing the following lines:
 --change the value shown in RED colours.It should be (width -1).
              signal random_num : std_logic_vector(3 downto 0);  
 --change the value shown in RED colours.It should be equal to 'width' of the output vector.
              uut: entity work.random generic map (width => 4) PORT MAP