Contact me for VHDL or Verilog projects and assignments

Thursday, March 11, 2010

Synthesis Error : More than 100% of Device resources are used

    Consider the below program.This program simply takes two 256 bit vectors and xor them to give a 256 bit output.

entity test is
port (  clk : in std_logic;
          in1 : in std_logic_vector(255 downto 0);
          in2 : in std_logic_vector(255 downto 0);
          out1 : out std_logic_vector(255 downto 0)
     );
end test;
architecture Behavioral of test is
begin
process(clk)
begin
if(clk'event and clk='1') then
out1 <= in1 xor in2;
end if;
end process;
end Behavioral;

      When you simulate the code,it will work properly.The outputs will come as expected.But when you try to synthesis the same code the following warning will come:
WARNING:Xst:1336 -  (*) More than 100% of Device resources are used.
      Now, why this warning has come?The code is hardly 20 lines.But the warning says "More than 100% of Device resources are used"!!! To know more about the warning open the "Synthesis Report".Just scroll down the report and you will see some details under the heading "Device utilization summary".This list shows the resources used by your program in the selected FPGA.Note down this line :
   " Number of bonded IOBs:                 769  out of    480   160% (*)   "
Here IOB means Input or Output blocks. We are using 769 IOB's out of 480 available ones.This was the reason for the warning.So how do we test the program.If the above program is your top module then there is no way that you can run it in FPGA.But if this program is just a component of some main module then you can check whether the code is synthesizable or not.Here is how you do it?Write the following code:

entity test_top is
port  ( clk : in std_logic );
end test_top;
architecture behavior of test_top is
    component test    --the module which ,I got warning for is declared as a component here.
    port(
         clk : in  std_logic;
         in1 : in  std_logic_vector(255 downto 0);
         in2 : in  std_logic_vector(255 downto 0);
         out1 : out  std_logic_vector(255 downto 0)
        );
    end component;
--declare the signals accordingly.
   signal in1 : std_logic_vector(255 downto 0) := (others => '0');
   signal in2 : std_logic_vector(255 downto 0) := (others => '0');
   signal out1 : std_logic_vector(255 downto 0);
begin
   uut: test port map (clk,in1,in2,out1);    --port map the component.
end behavior;
    Now when you synthesis the code you will not get any warnings or errors.Thus you have tested the design which was unable to do,when you tried to synthesis it directly.What I have done here is,I wrote a new entity with only one input - clk, by which I removed the over usage of IOB's.Then I gave my code,which has to be tested, as a component of this code.

Note :-The error  "More than 100% of Device resources are used" doesn't always means that you have to change your FPGA.Read the synthesis report carefully to check where the problem is.The above method is useful only for checking whether your sub-module is synthesizable or not.

1 comment:

  1. This method would save the IOB employee requiring the component and if so, this is implemntable in FPGA, thank in advance!

    ReplyDelete

Related Posts with Thumbnails