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Thursday, March 11, 2010

Synthesis Error : Signal is connected to multiple drivers

   Consider the following code:

entity test is
port (  clk1 : in std_logic;
          clk2 : in std_logic;
          out1 : out std_logic_vector(7 downto 0)
     );
end test;
architecture Behavioral of test is

signal out2: std_logic_vector(7 downto 0);
begin
out1 <= out2;

process(clk1)  
begin
if(clk1'event and clk1='1') then
out2 <= out2 + "00000001";   --increment by '1'
end if;
end process;

process(clk2)
begin
if(clk2'event and clk2='1') then
out2 <= out2 + "00000011" ;      -- --increment by '3'
end if;
end process;

end Behavioral;

   The above code can be successfully compiled without any errors or warnings.But when you try to synthesis it you will get the following errors:
ERROR:Xst:528 - Multi-source in Unit on signal <0>>; this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit on signal ; this signal is connected to multiple drivers.
...

ERROR:Xst:528 - Multi-source in Unit on signal ; this signal is connected to multiple drivers.
   
    This was the one of the most common errors I got, when I synthesized my first program.This error occurs when we try to change a signal in two different processes.As you can see from the above code the signal 'out2' is driven by two clocks,named clk1 and clk2.A multi-driven signal cannot be realized in hardware.If the clk1'event and clk2'event occurs at the same time then,the hardware doesn't know which statement to execute.That is why this kind of code is not synthesizable.And there is no way to solve this error.Only option is to change your logic in some way that you can get your things done without using a multi-driven signal.
    But one interesting thing is that,even if you don't get any errors during compilation, you will not get any simulation results with this code.The output signals will be "xx",which means "unknown".You can see the following warning in the simulation console:
Instance /xxx/uut/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).

Note :- Never change a signal in two different processes.This will give you a warning during simulation and will generate an error during synthesis.

3 comments:

  1. Hey,

    The error occurs with changing a signal in two different processes with different clock or two different processes with same clock as well.

    For example I have a top module, one component generates clock from the say master clock, assigns value to port on the master clock, then the port through top feeded in to the other component running on the master clock. The port signal is just used to assign value to another port there.
    Hope you get my point of view

    Reader

    ReplyDelete
  2. For simulation you can assign "00ZZ" in process A and "ZZ11" in process B and you will get "0011" instead of "XXXX".

    ReplyDelete
  3. But Some where I have read like std_logic is a resolved datatype so that It can resolve when there are multiple sources or drivers . Even though if it is just for simulation why we are using multiple drivers in simulation. Please give me clarity on this

    ReplyDelete

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