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Thursday, March 11, 2010

Synthesis warning : FF/Latch has a constant value of 0 in block

    Consider the following code snippet:

signal count : std_logic_vector(7 downto 0) :="00000000";
process(clk)
begin
if(clk'event and clk='1') then
count <= count+"00001000";
end if;
end process;

The above code will not generate any error or warnings during simulation but will give the following warnings during synthesis:
WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING : Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.


    So should you be worried about these warnings.Will the program work as expected on FPGA board? The answer can be YES or NO,depending upon your other parts of the program.For the above program the answer is "YES". If you look at the code,you can see that binary value "1000" is added to a  8 bit std_logic_vector which is initialized to zero.So in effect the LSB 3 bits of the signal 'count' will be same i.e. '0'.So during synthesis these signals are trimmed or removed as a part of optimization process.But still your code will work as it did during simulation.
   But this is not the case always.Sometimes you may not have written your code properly,considering all the possibilities and the signals which are actually needed may get trimmed.Then the program will fail to work on board.

Note :- Whenever you get the above warnings,check your program carefully and make sure that the signals which got trimmed are not needed for your logic to work.

1 comment:

  1. Hi. I'm new to VHDL and hardware design in general. Could you please explain how you would resolve the above problem? Thanks.

    ReplyDelete

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