VHDL coding tips and tricks: Synthesis warning : Node of sequential type is unconnected in block
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Thursday, March 11, 2010

Synthesis warning : Node of sequential type is unconnected in block

Consider the following program :

entity test is
port (   clk : in std_logic;
           data_in : out std_logic_vector(7 downto 0)    -- 8 bit output
         );
end test;
architecture Behavioral of test is
signal count : integer:=0;  --Remember that 'integer' 32 bit vector.
begin
--conv_std_logic_vector is a conversion function.
data_in <= conv_std_logic_vector(count,8);    --assigning output.
process(clk)
begin
if(clk'event and clk='1') then
count <= count+1;    --incrementing count.
end if;
end process;
end Behavioral;

    This module when simulated will work perfectly without any warnings or errors.But when synthesized it will give the following errors:
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
WARNING:Xst:2677 - Node of sequential type is unconnected in block .

...
...
WARNING:Xst:2677 - Node of sequential type is unconnected in block .

     So should you be worried about these warnings.Will the program work as expected on FPGA board?In this case you don't need to worry about these warnings.Check the code clearly.The signal 'count' is declared as an integer,whose default size is 32 bit.But your module output is only 8 bit.So in effect you are not using the bits 8 to 31 of signal 'count'.So during the synthesis the software will optimize the code so that it has minimum number of connections.That is why the warnings "node is unconnected in block".
   Now even though the program will work with such warnings what if you want to remove it?How will you get rid of such irritating warnings.Make a small change in the above code :
Replace "signal count : integer:=0;" with the following line :
"signal count : integer range 0 to 255:=0;"
What we are doing here is we are restricting the range of integer to values between 0 to 255.That is now signal 'count' is a 8 bit integer.Warnings will not come now.

Note :- Sometimes you can neglect warnings.Remember that warnings are not errors.They are some of the possible potential risks.But not always, they create a problem.

3 comments:

  1. It's a good idea if you are working with integer signals, but. What happened if you use std_logic_vector?
    I am adding 2 std_logic_vector signals with 24 bits, and I need to reduce the result to 18 bits. What can I do to make dissapear this warning? thanks.

    ReplyDelete
  2. Jose, why don't you try initializing the vector to zeros with others=>0. Then, if you are not using the latter 6 bits, they will be 0s and you won't have the warning.

    ReplyDelete
  3. In my case of this warning, I have a 32-bit slv coming into a module, and I'm only using a 6-bit slice of this vector. This leaves 26 unconnected 'nodes' that are inputs so I can't initialise/set them to anything in this module. Is there a way to somehow mark these as intentionally unused and avoid the warning, without changing any code outside this module?

    ReplyDelete