STD_LOGIC is defined in the library

**std_logic_1164**.This is a nine valued logic system.

It has 9 values: 'U', 'X', '0', '1', 'Z', 'W', 'L' ,'H' and '-'.

The meaning of each of these characters are:

U = uninitialized

X = unknown - a multisource line is driven '0' and '1' simultaneously (*)

0 = logic 0

1 = logic 1

Z = high impedance (tri state)

W = weak unknown

L = weak "0"

H = weak "1"

- = dont care

Type

**std_logic is unresolved**type because of 'U','Z' etc.It is illegal to have a multi-source signal in VHDL.So use 'bit' logic only when the signals in the design doesn't have multi sources.If you are unsure about this then declare the signals as std_logic or std_logic_vector,because then you will be able to get errors in the compilation stage itself.

But many of the operators such as shift operators cannot be used on 'std_logic_vector' type.So you may need to convert them to bit_vector before using shift operations.One example is given below:

--example of how to shift a std_logic signal : right shifting logically by 2 bits.

--count is std_logic_vector.

output <= To_StdLogicVector(to_bitvector(count) srl 2);

--to_bitvector converts Std_Logic_Vector to bit_vector.

--To_StdLogicVector converts bit_vector to Std_Logic_Vector.

**Note**:- Remember that use "BIT" logic type only when you are sure that the signals are NOT multi sourced.

BIT_VECTOR is an array of BIT's.Similarly STD_LOGIC_VECTOR is an array of std_logic type.

Good explanation ;)

ReplyDeleteSo, when you use std_logic type, it's easier to detect multisourced signal and correct if it needs to be corrected (it appears red in modelsim wave window by example).

std_logic is unresolved? Are you crazy? Do you know what "subtype std_logic is resolved std_ulogic" means?

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