VHDL coding tips and tricks: When and how to use "constant"?

Tuesday, March 9, 2010

When and how to use "constant"?

Here are some points about the keyword 'constant' in VHDL.

1)Constants are declared and initiliazed as shown below :
       constant const_name : std_logic_vector(3 downto 0):="1010";
2)A constant is an object that is assigned a value only once,normally when it is declared.This value cannot be changed later in the program.constants are used as a part of making more readable codes because by changing the value at only one point you can make a change throughout the program.
3)When a constant is declared in a package, its name and type must be specified.But the assignment can be done either as part of its declaration in the package or it can be given in the package body.To know more about packages click here.

Note :- Use constants whenever you are going to use a particular value at many places in your program.This will make your code more readable.

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