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Wednesday, April 14, 2010

What is a Gated clock and how it reduces power consumption?

    Gated clock is a well known method for reducing power consumption in synchronous digital circuits.By this method the clock signal is not applied to the flip flop when the circuit is in idle condition.This reduces the power consumption.
In a digital corcuit the power consumption can be accounted due to the following factors:
1) Power consumed by combinatorial logic whose values are changing on each clock edge 
2) Power consumed by flip-flops.
Of the above two, the second one contributes to most of the power usage.
A flip flop consumes power whenever the applied clock signal changes,due to the charging and discharging of the capacitor.If the frequency of the clock is high then the power consumed is also high.Gated clock is a method to reduce this frequency.

Consider the following VHDL code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity normalclk is
port( clk : in std_logic;
      load : in std_logic;
      i : in std_logic;
     o : out std_logic
      );    
end normalclk;


architecture Behavioral of normalclk is

BEGIN
process(clk)
begin
if(rising_edge(clk)) then
if(load ='1') then
o <= i;
end if;
end if;
end process;

end Behavioral;

The code if synthesized will look like this:(RTL schematic on the left side and technology schematic on the right side)
As you can see the clock is always applied to the flip flop and this results in considerable loss in power due to frequent charging and discharging of the capacitor.

Now let us modify the above piece of code , by using gated clock.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity gatedclk is
port( clk : in std_logic;
      load : in std_logic;
      i : in std_logic;
      o : out std_logic
      );    
end gatedclk;

architecture Behavioral of gatedclk is
signal gclk : std_logic;

BEGIN
gclk <= clk and load;
process(gclk)
begin
if(rising_edge(gclk)) then
o <= i;
end if;
end process;

end Behavioral;

The synthesized design will look like this:(RTL schematic on top and technology schematic on bottom)
   Note the AND operation between load and clk signal.Here the clock to the flip flop "FD" is said to be gated.The code's purpose is that ,the output has to change only when load is '1' at the rising edge of clock.So it is useless to drive the flip flop when the load signal is '0'.If the load signal changes very rarely, then the above gated clock code will result in a low power design.
   Apart from the advantage of reducing power consumption it has some disadvantages :
1) As you can see when you use gated clock, the buffer used in of type IBUF (input buffer) .But when the clock is not gated, synthesis tool uses BUFGP buffer ( which is faster and used normally as a buffer for clocks).This may result in a small delay.
2) In a synthesis point of view the gate controller takes more area and make the design more complicated.

2 comments:

  1. Xilinx has several guides talking about why this is a bad idea.

    This type of code is, unfortunantly, even taught in some college courses.

    The issue is that you've moved the clock out of the low-skew global clock routing. This isn't really that bad for most college designs -- 50MHz and slower designs are very easy to do on a V5. but once you look at 250MHz+ designs, you start to notice that 2ns+ of skew is actually significant.

    Another issue is that you must make sure the clock enable meets setup/hold times for the clock. otherwise (with skew) some elements may get clocked, others might not. In this case, that means that "load" must be synchronous to clk.

    for an FPGA, its probably better to use BUFGMUX, BUFG_CTRL, or BUFG_CE, as these use the global routing. the comments about setup/hold for the "enable" still apply though.

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  2. The principle of using gated clocks comes originally from ASIC design where the designer has full control over signal path delays, setup and hold times, etc. In an FPGA however, i would rather not use it unless one is begging for trouble.
    First of all, it's not needed. Using the enable input of the flip-flop will archive the same but the timing analysis will not be compromised. Concerning the power consumption, it's the switching of the flip-flop which uses power. So it terms of power consumption it makes no difference disabling the clock or just not enabling the flip-flop.
    Second, combinatorial logic doesn't have a clock, it changes if the input values change and this input values normally come from flip-flops. If the flip-flop doesn't change the combinatorial logic won't change either.

    Beside the fact that a design with gated clocks will use more resoures as you've shown in the RTL schematic, there's a much more important point. You'r timing behaviour can/will become unpredictable. Because in an FPGA it's not only about the RTL level, there are also the path delays after Place&Route. The global lines in an FPGA have a kind of "fixed" and predictable delay. Using combinatorial logic to gate the clock means using some input signal to control/gate the clock. And this signal is routed via the normal routing network, which means the timing will change with every P&R. So a perfectly working design might not work the next time you change something and go through synthesis and P&R again, even if your change is completely unrelated to the part with the gated clock.

    So unless you want to go through really nasty debugging sessions with a high propability of not finding the cause of your problems,stay away from gated clocks in FPGAs and other programmable devices!

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