VHDL coding tips and tricks: KEEP HIERARCHY : A synthesis option in XST.
Contact me for VHDL or Verilog projects and assignments

Saturday, July 24, 2010

KEEP HIERARCHY : A synthesis option in XST.

    For those who doesnt know about what this topic about, I am trying to talk about the "keep hierarchy" option available in the xilinx synthesis options.This option along with many other options can be viewed or changed by going through the following steps:
1)Right clicking on the synthsis-XST in the processes tab.
2)Click on Properties to get the window shown below in the image.
3)Click on synthesis options in the category side.
4)Look down on the right side of the window for the "Keep Hierarchy" option and change it to No or yes.

Now I want to list out some points about this "Keep Hierarchy" option:
1)This particular option is used for designs which has more than one VHDL code in the design.I mean a design which may contain a top module and some components.
2)Whenever the XST starts synthesis process it tries to optimize the design for the particular selected  architecture.Now when we select the option as "keep hierarchy yes" then XST will only optimize by taking each component at a time.This is faster in terms of synthesis time but optimization has limited reach.
3)when we select the option as "keep hierarchy no" then XST will optimize the whole design at one single pass.This is time consuming but results in better optimization results.

Let me prove the above points with the help of an example.The code I have used is already published in
this blog.It is "4 bit Synchronous UP counter(with reset) using JK flip-flops".

I copied these codes into a new project directory and synthesized the design using the option "Keep Hierarchy: yes" first. The following synthesis results were showed up:

Device utilization summary:
---------------------------
Selected Device : 5vlx30ff324-3

Slice Logic Utilization:
 Number of Slice Registers:               4  out of  19200     0%
 Number of Slice LUTs:                    6  out of  19200     0%
    Number used as Logic:                 6  out of  19200     0%

Slice Logic Distribution:
 Number of LUT Flip Flop pairs used:     10
   Number with an unused Flip Flop:       6  out of     10    60%
   Number with an unused LUT:             4  out of     10    40%
   Number of fully used LUT-FF pairs:     0  out of     10     0%
   Number of unique control sets:         4

Minimum period: 1.565ns (Maximum Frequency: 639.141MHz)


Now I ran the XST again with the option "Keep Hierarchy: no".This time I got different results:

Slice Logic Utilization:
 Number of Slice Registers:               4  out of  19200     0%
 Number of Slice LUTs:                    4  out of  19200     0%
    Number used as Logic:                 4  out of  19200     0%

Slice Logic Distribution:
 Number of LUT Flip Flop pairs used:      8
   Number with an unused Flip Flop:       4  out of      8    50%
   Number with an unused LUT:             4  out of      8    50%
   Number of fully used LUT-FF pairs:     0  out of      8     0%
   Number of unique control sets:         3

Minimum period: 1.101ns (Maximum Frequency: 908.348MHz)

You can see that there is a 300 MHz increase in the operating frequency when the hierachy is not kept.Even the resource usage become minimal in the second case.
Another observation you can make is from the Technology Schematic viewer in XST. For the first case the RTL viewer will show you sub blocks in the main block which may contain LUT's and flipflops.But in the second case there wont be any sub blocks available at all.Only LUT's and flipflops will be available directly under the main block.This is what I meant by saying that the XST will optimize the design taking as a whole.You can verify this yourself by clicking on the "View Technology schematic" option under synthesis-XST.

1 comment:

  1. Your example is too simple. In my case, keeping hierarchy was slower by 20%, as the final design had to route signals further on the FPGA fabric, and use higher fan-outs.

    I think that not keeping hierarchy only makes sense if you are running short on resources...

    ReplyDelete