VHDL coding tips and tricks: Design and simulation of BRAM using Xilinx Core generator
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Thursday, October 7, 2010

Design and simulation of BRAM using Xilinx Core generator

   BRAM(Block Random access memory) is an advanced memory constructor that generates area and performance-optimized memories using embedded block RAM resources in Xilinx FPGAs.I hope you have already gone through the Core generator introductory tutorial before.If you haven't please read those articles here.

   For creating a custom BRAM, run Core Generator software:
1)Create a new project and select the required device details for which you want to generate the model.
2)Select "View by Function" category.
3)Select "Memories & Storage Elements" and then "RAMs & ROMs".
4)Double click on the "Block Memory Generator(version 4.1)" and a new window will open similar to the one shown below:

   Now we can start customizing the BRAM as per our requirements. For testing purpose I am going to generate a single port RAM with size 256*8 bit size.The settings I have used are given below:
1)Component Name:BRAM_test
2)Uncheck "Use byte write enable".
3)Select the algorithm as "Low Power".
4)Go to next page.
5)Select write width and read width as "8".
6)Set write depth as "256" which is the number of locations in RAM.
7)Operating mode is "No change".
8)Go to next page.
9)Uncheck all options except "Fill Remaining memory locations" with "0".If you want you can initialize the RAM with a coe file also. Using coe file to initialize BRAM will be explained through another article.
10)Keep other options as "default" and click on "generate" button.The software will now start generating the necessary files such as ngc,vhd,xco etc.

Now close core generator software and open Xilinx ISE.Create a new project with the same device details you have used to create the core generator project.Add BRAM_test.xco or BRAM_test.ngc to this project. Create a new VHDL file in this project directory and name it as BRAM_main.vhd. This code will act like a testbench code for testing the BRAM you have generated. In general you can see how to make it work after going through this example.

The contents of BRAM_main.vhd is displayed below:

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity testbench is  
end testbench;

architecture Behavioral of testbench is

--temporary signal declarations.
signal ena : std_logic := '0';
signal wea : std_logic_VECTOR(0 downto 0):="0";
signal addra,dina,douta : std_logic_VECTOR(7 downto 0) := (others => '0');
signal clk : std_logic := '0';

begin

--Instantiating BRAM.
BRAM : entity work.BRAM_test
    port map(
    clka => clk,  --clock for writing data to RAM.
    ena => ena,   --Enable signal.
    wea => wea,   --Write enable signal for Port A.
    addra => addra, --8 bit address for the RAM.
    dina => dina,   --8 bit data input to the RAM.
    douta => douta);  --8 bit data output from the RAM.

--Simulation process.
process
begin
    wait for 1 ns;
    --Writing to all the memory locations of the BRAM.Set wea "1" for this.
    for i in 0 to 255 loop
        ena <= '1';  --Enable RAM always.
        wea <= "1";
        wait for 2 ns;
        addra <= addra + "1";
        dina <= dina + "1";
    end loop;  
    addra <= X"00";  --reset the address value for reading from memory location "0"
    --reading all the 256 memory locations in the BRAM.
    for i in 0 to 255 loop
        ena <= '1';  --Enable RAM always.
        wea <= "0";
        wait for 2 ns;
        addra <= addra + "1";
    end loop;
    wait;
end process;   

--Clock generation - Generates 500 MHz clock with 50% duty cycle.
process
begin
    clk <= '1';
    wait for 1 ns;  --"ON" time.
    clk <= '0';
    wait for 1 ns;  --"OFF" time.
end process;   
   
end Behavioral;

The signals used in the port mapping can be checked by viewing the BRAM_test.vhd file generated by the core generator tool.Simply copy all those signal names for instantiating the BRAM component in your design.Also remember that you have to either add the .xco file or the .ngc file to the project, for simulation to work.

The simulated waveform is shown below:


Note :- This is the most simplest BRAM. The design will get complicated when you go from single port to dual port RAM's.But the basic idea remains the same.By reading the documentation supplied by Xilinx you can explore more settings used in the GUI tool.For testing purpose I have used Xilinx ISE 12.1 version and BRAM version 4.1. The options in the core generator tool may vary slightly depending on the version you are using.

3 comments:

  1. i have implemented ur design @ ise , i am getting following error -
    "Pack:198 - NCD was not produced. All logic was removed from the design.
    This is usually due to having no input or output PAD connections in the
    design and no nets or symbols marked as 'SAVE'. You can either add PADs or
    'SAVE' attributes to the design, or run 'map -u' to disable logic trimming in
    the mapper. For more information on trimming issues search the Xilinx
    Answers database for "ERROR:Pack:198" and read the Master Answer Record for
    MAP Trimming Issues."

    ReplyDelete
  2. I did exactly what you did, and now I have the following warnings:

    WARNING:ProjectMgmt - Duplicate Design Unit 'BRAM_test' found in library 'work'
    WARNING:ProjectMgmt - "C:/Users/tam/Desktop/BRAM/BRAM_test_synth.vhd" line 64 (active)
    WARNING:ProjectMgmt - "C:/Users/tam/Desktop/BRAM/BRAM_test.vhd" line 43

    And I also have the following errors:

    Map:116 - The design is empty. No processing will be done.
    Map:52 - Problem encountered processing RPMs.

    Can you help me to fix this? thank you!

    ReplyDelete
  3. I did exactly what you did, and now I have the following warnings:

    WARNING:ProjectMgmt - Duplicate Design Unit 'BRAM_test' found in library 'work'
    WARNING:ProjectMgmt - "C:/Users/tam/Desktop/BRAM/BRAM_test_synth.vhd" line 64 (active)
    WARNING:ProjectMgmt - "C:/Users/tam/Desktop/BRAM/BRAM_test.vhd" line 43

    And I also have the following errors:

    Map:116 - The design is empty. No processing will be done.
    Map:52 - Problem encountered processing RPMs.

    Can you help me to fix this? thank you!

    ReplyDelete