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Thursday, June 28, 2012

How to Mix VHDL and Verilog files in your design

Sooner or later you will come across this question in your FPGA design career. There are times you found the right modules in the web, but couldn't use it just because you are using a different HDL. But you dont need to be disappointed. Instantiating VHDL components in Verilog modules, or vice versa is a simple process. Let me show it with an example.

Case 1 -   Instantiating VHDL components in Verilog modules:

  For example sake, take the synchronous D flip flop vhdl code I have written some time before. Suppose I want to write a Verilog module in which I want to instantiate two D- flipflops. Without worrying, you can simply instantiate it like you do it for a verilog module. See the code:

module test(
    output [1:0] Q,
    input Clk,
    input CE,
    input RESET,
    input SET,
    input [1:0] D
    );

example_FDRSE(Q[0],Clk,CE,RESET,D[0],SET);
example_FDRSE(Q[1],Clk,CE,RESET,D[1],SET);

endmodule



Case 2 -   Instantiating Verilog modules in VHDL components:


  This case is also straightforward. You don't need to worry about anything. Just instantiate as you normally do it with a vhdl file.

Take this verilog module for instance,

module a1(
    output Q,
    input [1:0] D
    );

and(Q,D[0],D[1]);

endmodule




A simpe vhdl code for instantiating this Verilog code can look like this:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity test is 
   port(
      Q : out std_logic_vector(1 downto 0);
      D :in  std_logic_vector(3 downto 0)
   );
end test;

architecture Behavioral of test is 

component a1 is 
   port(
      Q : out std_logic;
      D :in  std_logic_vector(1 downto 0)
   );
end component;

begin  

a11 : a1 port map(Q(0),D(1 downto 0));
a22 : a1 port map(Q(1),D(3 downto 2));

end Behavioral;



Never thought mixing vhdl and verilog files were so easy? But it is!

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