tag:blogger.com,1999:blog-2050962176404305705.post1557165928532387892..comments2024-03-06T20:16:12.046+05:30Comments on VHDL coding tips and tricks: Triangular Wave generator in VHDLvipinhttp://www.blogger.com/profile/17675762038225600067noreply@blogger.comBlogger3125tag:blogger.com,1999:blog-2050962176404305705.post-13113851039637656192019-04-21T15:48:01.931+05:302019-04-21T15:48:01.931+05:30I have an error :
Signal count cannot be synthesiz...I have an error :<br />Signal count cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.<br />--> <br />how to do please !Anonymoushttps://www.blogger.com/profile/02807879473700099090noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-9332803107212808582019-04-10T01:00:09.964+05:302019-04-10T01:00:09.964+05:30Why are you intiallize the count2 with 126 and 129...Why are you intiallize the count2 with 126 and 129 onlyAnonymoushttps://www.blogger.com/profile/06511773653232751153noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-12977439366192909642016-02-19T16:48:45.729+05:302016-02-19T16:48:45.729+05:30ProjectMgmt:806 - "F:/aprojct/ritu/ritttuu/tt...ProjectMgmt:806 - "F:/aprojct/ritu/ritttuu/ttr_1.vhd" Line 60. Syntax error near "Testbench".<br /><br />how to solw it?Ritu singhhttps://www.blogger.com/profile/00316628677573818548noreply@blogger.com