tag:blogger.com,1999:blog-2050962176404305705.post4124043760120514889..comments2024-03-06T20:16:12.046+05:30Comments on VHDL coding tips and tricks: VHDL: Can you change a signal at both positive and negative edges of the clock?vipinhttp://www.blogger.com/profile/17675762038225600067noreply@blogger.comBlogger3125tag:blogger.com,1999:blog-2050962176404305705.post-28336314189582602852016-10-02T10:40:48.474+05:302016-10-02T10:40:48.474+05:30this will work fine because you havnt used it as a...this will work fine because you havnt used it as a clock. you are not doing edge detection here. but only level detection of A and B.<br />vipinhttps://www.blogger.com/profile/02146017720228354842noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-11657130125411580662012-10-31T09:06:36.190+05:302012-10-31T09:06:36.190+05:30actually in spartan and virtex series board do not...actually in spartan and virtex series board do not have dual edge sensitive flipflop. Once hardware is unavailable how could u implement it. But I got an information that in cool runner series board u can implement this logic. <br />But u can consider two separate process where one is rising edge sensitive and other one is negative edge sensitive rourabhttps://www.blogger.com/profile/12658101906469262296noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-38615324094791471172011-01-08T21:04:05.123+05:302011-01-08T21:04:05.123+05:30ok but what about:
bla : PROCESS(A, B)
BEGIN
if...ok but what about:<br /><br />bla : PROCESS(A, B)<br />BEGIN<br /> if A = '1' then<br /> C <= B;<br /> else<br /> C <= (others => 'Z');<br /> end if;<br />END PROCESS;<br /><br />that synthesizes fine for meArsenihttps://www.blogger.com/profile/16105975554539624872noreply@blogger.com