tag:blogger.com,1999:blog-2050962176404305705.post5938252491309678448..comments2024-03-06T20:16:12.046+05:30Comments on VHDL coding tips and tricks: Random number generator in VHDL(cont from a prev post)vipinhttp://www.blogger.com/profile/17675762038225600067noreply@blogger.comBlogger5125tag:blogger.com,1999:blog-2050962176404305705.post-25740839853854538382014-06-08T20:38:43.073+05:302014-06-08T20:38:43.073+05:30Can you please post the code in this post itself? ...Can you please post the code in this post itself? Opencores asks for registration and confirmation takes another two or more days to complete!<br />Thanks!<br />sndn_shr@yahoo.comසඳූhttps://www.blogger.com/profile/07700339871574294263noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-75949776733244598492011-09-13T20:28:34.470+05:302011-09-13T20:28:34.470+05:30Mr. Vipin,
I have implemented this module in orde...Mr. Vipin,<br /><br />I have implemented this module in order to produce white noise as an audio source, but the frequency response I am getting is not flat.<br /><br />The low end is cut off and rises inverse-exponentially to a flat PSD at around 8kHz (Fs = 44100Hz). Therefore the white noise sounds very high-pass filtered.<br /><br />Do you have any idea why this is happening? I have tried with different word lengths and seed values without any luck.<br /><br />Here is a link showing the PSD:<br />http://www.photostand.co.za/images/934h5nswi8annoh10xr.png<br /><br />Thank you!Matthttps://www.blogger.com/profile/04300470648892550016noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-42835740521774921922010-12-19T00:27:02.703+05:302010-12-19T00:27:02.703+05:30can u please provide me a code for binary multipli...can u please provide me a code for binary multiplier.......<br />thanx in advancekrakkathttps://www.blogger.com/profile/05012026112106053532noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-83080875087409536352010-08-17T18:50:40.353+05:302010-08-17T18:50:40.353+05:30@Chris: As per your comments I have modified the c...@Chris: As per your comments I have modified the code a little and have uploaded the new version. Please check it out.<br />I have removed the input "out_enable" as it is not necessary.<br />Also the setting the seed functionality is made synchronous instead of asynchronous.vipinhttps://www.blogger.com/profile/17675762038225600067noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-44919797248982349192010-08-08T12:05:40.605+05:302010-08-08T12:05:40.605+05:30This code is actually done in a fairly nice way --...This code is actually done in a fairly nice way -- at least from the perspective of the function. My biggest concern is the async load and async enables. Both can be async, which is almost always a bad idea. Async signals need VERY careful attention to avoid errors. They are particularly good at destroying state machines and control logic. <br /><br />This is because there is data and clock skew, thus each LUT+FF that uses the async signal as an input will receive each bit of the signal at a slightly different time. (or will get a clock edge at a slightly different time)<br /><br />For the LFSR case, initializing to something like 0001 can cause the design to fail. If load is deasserted near a clock edge (at any clock rate), then the lsb might shift in a 0 (if load = 0 at this FF). If the upper bits still have load asserted (eg, there is a longer delay from load to these FF's), then they will stay 0's. Thus the LFSR will transition from 0001 to 0000. At this point, the LFSR is stuck.<br /><br />Also, async loads are often used in interview questions as something to avoid.Unknownhttps://www.blogger.com/profile/08696534976347075173noreply@blogger.com