tag:blogger.com,1999:blog-2050962176404305705.post6499272431669804020..comments2024-03-06T20:16:12.046+05:30Comments on VHDL coding tips and tricks: Sequence detector using state machine in VHDLvipinhttp://www.blogger.com/profile/17675762038225600067noreply@blogger.comBlogger24125tag:blogger.com,1999:blog-2050962176404305705.post-83411554815502193342018-11-12T14:17:50.005+05:302018-11-12T14:17:50.005+05:30Can you please send the code for moore sequence de...Can you please send the code for moore sequence detector for sequence-0111010Anonymoushttps://www.blogger.com/profile/18199251605196215641noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-44289212543452676882018-09-13T14:29:25.395+05:302018-09-13T14:29:25.395+05:30Which book is good for vhdl
Which book is good for vhdl<br />Anonymoushttps://www.blogger.com/profile/00068335668802992357noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-17410212482266994512018-05-27T22:37:57.464+05:302018-05-27T22:37:57.464+05:30What if I wanted to detect this sequence five time...What if I wanted to detect this sequence five timesAnonymoushttps://www.blogger.com/profile/14912926962442528541noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-88334936057373213512017-01-27T15:42:12.876+05:302017-01-27T15:42:12.876+05:30hi i have the same problem, can`t see state change...hi i have the same problem, can`t see state change, the state is always A ..<br />can you help me, please ?Temahttps://www.blogger.com/profile/08804353170852402238noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-90956525802192923682016-03-23T14:39:38.852+05:302016-03-23T14:39:38.852+05:30I am eager to see the answer. I want to to see tha...I am eager to see the answer. I want to to see that too.Anonymoushttps://www.blogger.com/profile/02715192906024405226noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-65381523152552916072015-01-21T20:19:34.708+05:302015-01-21T20:19:34.708+05:30if it is a overlapping sequence in the last state ...if it is a overlapping sequence in the last state D after encountering '1' it must go to state B RIGHT?Please correct me if I am wrong Sohail Sirajhttps://www.blogger.com/profile/01725882260421706550noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-34494412561672564262014-09-04T12:16:44.644+05:302014-09-04T12:16:44.644+05:30Hello to everybody . Please tell me what i must do...Hello to everybody . Please tell me what i must do for having "state" in TEST BENCH SIMULATION ??? Thanks ... Anonymoushttps://www.blogger.com/profile/11192241439219327506noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-81903077742153858482013-10-24T14:56:35.742+05:302013-10-24T14:56:35.742+05:30thank u bt in simulation we are not getting 's...thank u bt in simulation we are not getting 'state' ;Anonymoushttps://www.blogger.com/profile/05047739135748562929noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-81612841542791902192012-08-09T17:44:35.296+05:302012-08-09T17:44:35.296+05:30Hi, the program you have mentioned above seems to ...Hi, the program you have mentioned above seems to me helpful to detect ADS-S signal(https://docs.google.com/document/d/1EzR8wpxjFJhmnaxeSt7_6DNqb-bFPda8emZF6W1kIhI/edit?pli=1) for my project.<br />All I need to detect only pattern of the signal (only 10 microsecond from the beginning not the entire 120 microsecond in attached figure).<br /><br />As I am very new to VHDL and so difficult to proceed.<br />Can I get some more Idea how I can proceed to do simulation to detect this signal?<br /><br />Thanks in Advance<br />SheikhAnonymousnoreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-9240613693139355982012-07-01T15:48:16.242+05:302012-07-01T15:48:16.242+05:30@sabin : contact me using the contact form. I can ...@sabin : contact me using the contact form. I can help for a fee.vipinhttps://www.blogger.com/profile/17675762038225600067noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-88344795789377923952012-07-01T13:39:15.322+05:302012-07-01T13:39:15.322+05:30in the test bench i think is a mistake.... it didn...in the test bench i think is a mistake.... it didn't show the state signal... can you help me to fix the problem... i try to do something but the signal state in simulation is block on state A... some help someone?Anonymoushttps://www.blogger.com/profile/13670748443849568303noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-77306277393015730152012-06-28T16:04:21.501+05:302012-06-28T16:04:21.501+05:30@beast_boy : Contact me using the contact form and...@beast_boy : Contact me using the contact form and we will discuss about it.vipinhttps://www.blogger.com/profile/17675762038225600067noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-5108507603136308552012-06-28T16:01:07.895+05:302012-06-28T16:01:07.895+05:30please send me the state diagram with the necessar...please send me the state diagram with the necessary explanation for the below Question.on my email id (the.beast.master.007@gmail.com)<br />A sequential network has on input (X) and two outputs (Z1 and Z2). An output Z1=1 occurs every time the input sequence 010 is completed provided that the sequence 100 has never occurred.an output Z2=1 occurs every time the iniput sequence 100 is completed. Note that once a Z2=1 output has occurred, Z1=1 can never occur,but not vice versa.<br />a).Derive a mealy state graph and table with a minimum number of states (8 states).beast_boyhttps://www.blogger.com/profile/11841067956883646034noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-74333874005782582652012-02-22T11:07:35.676+05:302012-02-22T11:07:35.676+05:30want sequence detector for 0100 and 1000 sequences...want sequence detector for 0100 and 1000 sequencesSWETHAhttps://www.blogger.com/profile/02272328725414308536noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-83217665699223506332012-01-03T18:41:15.158+05:302012-01-03T18:41:15.158+05:30i want to ask...when i run the testbench and this ...i want to ask...when i run the testbench and this error come out : Error (10533): VHDL Wait Statement error at blog_cg.vhd(26): Wait Statement must contain condition clause with UNTIL keywordqishttps://www.blogger.com/profile/11687474939728390788noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-38842996777878797172011-11-30T21:59:21.880+05:302011-11-30T21:59:21.880+05:30Hai
I have project in vhdl to be completed with...Hai<br /> I have project in vhdl to be completed within next week.The project is to decode irig b pulses.pls help me in doing that <br /><br />maheshMahesh Nairhttps://www.blogger.com/profile/03289743140730436046noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-84639819327242349892011-06-17T07:32:28.357+05:302011-06-17T07:32:28.357+05:30@sonica : I think you can find the answer in any g...@sonica : I think you can find the answer in any good digital design book. The above example deals with a non overlapping sequence. So draw the state machine in a similar way.Once you have the state machine(which is the most important step) coding it in vhdl is a very easy process.vipinhttps://www.blogger.com/profile/17675762038225600067noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-90009311912382803522011-06-17T07:30:03.109+05:302011-06-17T07:30:03.109+05:30@Leandro : Really good question and observation. Y...@Leandro : Really good question and observation. You can use this type of design in all cases.<br />See the sensitivity list in both the processes. In this design it has Clk.So in each clk edge it will check and change the state.<br />But in the second code, the sensitivity list contains only next state and input. Which means that if they remain the same for some reason(depends on your state machine design) then the process statemnent may not evaluate in every clock cycle.vipinhttps://www.blogger.com/profile/17675762038225600067noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-51221783756019064762011-06-17T06:07:34.666+05:302011-06-17T06:07:34.666+05:30When should I use the state machine design used in...When should I use the state machine design used in this example and when should I use the design used in http://vhdlguru.blogspot.com/2010/04/how-to-implement-state-machines-in-vhdl.html?<br /><br />It seems to me that in this example you change the current state in the same clock as it's verified, but in the other one you let it wait to change in the next clock. Is my interpretation correct?Leandro Limahttps://www.blogger.com/profile/17085901057006527683noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-92036563413344117582011-06-05T18:26:00.959+05:302011-06-05T18:26:00.959+05:30How to draw the internal architecture of 4 bit non...How to draw the internal architecture of 4 bit non overlapping sequence detector????sonicahttps://www.blogger.com/profile/06018841328579124074noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-26015455778452892602011-05-12T22:07:51.825+05:302011-05-12T22:07:51.825+05:30@karan : Read any digital book for the state diagr...@karan : Read any digital book for the state diagram for overlapping sequence detector.<br />For converting the state diagram into a vhdl code, you can use the same concept used in this post.vipinhttps://www.blogger.com/profile/17675762038225600067noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-10153858131633985672011-05-12T20:19:32.277+05:302011-05-12T20:19:32.277+05:30What would be the state diagram for an overlapping...What would be the state diagram for an overlapping sequence? What is the difference?KARANhttps://www.blogger.com/profile/15727961227689034874noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-48962080162827651322011-02-08T09:36:10.273+05:302011-02-08T09:36:10.273+05:30@foam : thanks for the note. As you said, it shoul...@foam : thanks for the note. As you said, it should be process(clk,reset).vipinhttps://www.blogger.com/profile/17675762038225600067noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-59539564314390830662011-02-08T09:26:18.556+05:302011-02-08T09:26:18.556+05:30In process(clk) - reset is missing from the sensit...In process(clk) - reset is missing from the sensitivity list.Unknownhttps://www.blogger.com/profile/12885116348223545271noreply@blogger.com