tag:blogger.com,1999:blog-2050962176404305705.post73645291178365874..comments2024-03-06T20:16:12.046+05:30Comments on VHDL coding tips and tricks: VHDL: What are BIT, STD_ULOGIC and STD_LOGIC data types?vipinhttp://www.blogger.com/profile/17675762038225600067noreply@blogger.comBlogger1125tag:blogger.com,1999:blog-2050962176404305705.post-55381275038338520632010-05-11T15:02:26.743+05:302010-05-11T15:02:26.743+05:30Good explanation ;)
So, when you use std_logic typ...Good explanation ;)<br />So, when you use std_logic type, it's easier to detect multisourced signal and correct if it needs to be corrected (it appears red in modelsim wave window by example).Unknownhttps://www.blogger.com/profile/08128646462419425939noreply@blogger.com