tag:blogger.com,1999:blog-2050962176404305705.post7746628624611286225..comments2024-03-06T20:16:12.046+05:30Comments on VHDL coding tips and tricks: Clock Frequency converter in VHDLvipinhttp://www.blogger.com/profile/17675762038225600067noreply@blogger.comBlogger6125tag:blogger.com,1999:blog-2050962176404305705.post-68714460365381760292016-11-28T12:49:01.560+05:302016-11-28T12:49:01.560+05:30Hi i have 48MHz clock frequency anda i have to con...Hi i have 48MHz clock frequency anda i have to conver it to 20 MHz.<br />But 48/20= 2.4 so it is not an integer what can be done to do this?<br /><br />Thanks for your help Anonymoushttps://www.blogger.com/profile/17396746034429351422noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-64003120691974471742016-04-13T20:16:34.803+05:302016-04-13T20:16:34.803+05:30Hi, thanks for your examples.
I simplified your co...Hi, thanks for your examples.<br />I simplified your code and added reset signal as below:<br /><br />architecture Behavioral of main is<br />signal clk_div : STD_LOGIC := '0';<br />signal scnt : INTEGER := 2; <br />begin<br /> clk_div_proc: process(clk, rst) <br /> variable count : INTEGER := 0;<br /> begin<br /> if rst = '1' then<br /> clk_div <= '0';<br /> count := 0;<br /> elsif( rising_edge(clk) ) then<br /> if(count < scnt/2-1) then<br /> count := count + 1;<br /> else<br /> clk_div <= not clk_div;<br /> count := 0;<br /> end if;<br /> end if;<br /> end process;<br /> <br />end Behavioral;<br /><br />Best regards.Anonymoushttps://www.blogger.com/profile/11593740087588801146noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-27402886838499546822015-11-17T15:47:29.922+05:302015-11-17T15:47:29.922+05:30divide_value = (Frequency of Clk) / (Frequency of ...divide_value = (Frequency of Clk) / (Frequency of Clk_mod).<br /><br />so divide_value = 1000000/1000 = 1000.<br />vipinhttps://www.blogger.com/profile/02146017720228354842noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-29044314802651532612012-07-12T17:52:36.372+05:302012-07-12T17:52:36.372+05:30how can we write a code for the conversion of 1mhz...how can we write a code for the conversion of 1mhz to 1khz.divya pahwahttps://www.blogger.com/profile/09634240273164478541noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-86048432885150462622011-04-05T15:14:45.861+05:302011-04-05T15:14:45.861+05:30Very good post. Thanks again. For odd integer cloc...Very good post. Thanks again. For odd integer clock division the duty cycle isn't 50% though.Ravi Ramachandranhttps://www.blogger.com/profile/04547041735286266795noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-13465677636367531452011-03-28T17:49:47.124+05:302011-03-28T17:49:47.124+05:30Again, as in previous posts, your code results in ...Again, as in previous posts, your code results in clocks being taken of the low-skew global clock paths in the device. This is bad and as the previous commenter pointed out, WILL give problems at high frequencies.<br /><br />A better solution is to use a downsampled clock enable on your blocks. In this way the clock is still on the low-skew paths and you will make timing at high frequencies.Jaco Naudehttps://www.blogger.com/profile/01792673928589326803noreply@blogger.com