tag:blogger.com,1999:blog-2050962176404305705.post8495369170266704309..comments2024-03-06T20:16:12.046+05:30Comments on VHDL coding tips and tricks: VHDL: Synthesisable Code for Finding Square Root (With Testbench!)vipinhttp://www.blogger.com/profile/17675762038225600067noreply@blogger.comBlogger13125tag:blogger.com,1999:blog-2050962176404305705.post-22543123713572803052020-12-22T17:41:13.926+05:302020-12-22T17:41:13.926+05:30you can make a shift left for the number 50 by 8 b...you can make a shift left for the number 50 by 8 bits and after the sqrt shift the result by 4 bits right <br />so you will get the value you need Anonymoushttps://www.blogger.com/profile/03768835354997056027noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-75682406238225910062019-12-27T15:24:13.489+05:302019-12-27T15:24:13.489+05:30It works, just need to use it in in package.It works, just need to use it in in package.Anonymoushttps://www.blogger.com/profile/09387560038043097986noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-52630184482453498132016-10-14T00:25:16.681+05:302016-10-14T00:25:16.681+05:30Does your code gives the output for non perfect sq...Does your code gives the output for non perfect square????? ..i.e; sqrt (50)= 7.07Anonymoushttps://www.blogger.com/profile/04731895406784788178noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-14166524883099122132016-02-07T21:15:52.552+05:302016-02-07T21:15:52.552+05:30Could this code be easily adapted to deal with 32 ...Could this code be easily adapted to deal with 32 bit fixed point numbers?Anonymoushttps://www.blogger.com/profile/03651024823811912590noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-73380766703433377142014-03-14T13:48:26.479+05:302014-03-14T13:48:26.479+05:30to bedri pleaseto bedri pleaseAnonymoushttps://www.blogger.com/profile/15619363752568080648noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-46146548112435551382014-03-14T13:29:40.296+05:302014-03-14T13:29:40.296+05:30Hi, i have the same problem with you. If you find ...Hi, i have the same problem with you. If you find a solution, please write for me. I need help.Anonymoushttps://www.blogger.com/profile/15619363752568080648noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-22414964496477972572013-06-24T15:55:56.432+05:302013-06-24T15:55:56.432+05:30I'm trying to use your code in my application ...I'm trying to use your code in my application with using Altera DE2. In my system fpga gets adc out from GPIO pins. Then fpga have to calculate sqrt. I have been using fixed_pkg.vhdl. When i send any fixed point number to your function after conversion to fixed point to unsigned, it works. But when i send the adc value, it doesn't. And says "Error: In lpm_divide megafunction, LPM_WIDTHN must be less than or equals to 64". Could you please help or advise something to me?<br />bedrihttps://www.blogger.com/profile/17099048193115909379noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-71582500989730453312012-11-14T13:43:28.376+05:302012-11-14T13:43:28.376+05:30This code is working. But if you still need help r...This code is working. But if you still need help regarding anything I can help for a fee. <br />vipinhttps://www.blogger.com/profile/17675762038225600067noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-4462630945720991752012-11-14T13:42:11.199+05:302012-11-14T13:42:11.199+05:30the error came from function.... so, plz check it ...the error came from function.... so, plz check it and reply to me.........Anonymoushttps://www.blogger.com/profile/07625765729656815561noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-37718340090324424842012-02-16T10:03:32.433+05:302012-02-16T10:03:32.433+05:30while execution it is giving error . that is expec...while execution it is giving error . that is expecting entity or architecture near the function<br /><br /><br /><br /><br />with regards ,<br />nagaraja.vnagarajahttps://www.blogger.com/profile/09647089396737699473noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-10606297403933808112010-05-13T20:08:37.289+05:302010-05-13T20:08:37.289+05:30@thomas : Good Question.
As I am using a function ...@thomas : Good Question.<br />As I am using a function for the square root operation,there is no clock involved.It is a purely a combinational circuit.When synthesised Xilinx ISE uses LUT's(Look up tables) and some MUX'x for implementing it in hardware.<br />If you try synthesising it yourself you can see that a group of LUT's and MUX'x are connected in a cascaded fashion.This means that the logic written inside 'for loop' is implemented 15 times to realize the logic without clock.As you can see that this uses so much resources,but using functions is an easy way to write codes.<br />If you are concerned about the over use of logic gates, use a clock to implement the logic.This may reduce the logic gate usage by approximately 15.<br />(Note :- Shifting is not done in parallel here.)vipinhttps://www.blogger.com/profile/17675762038225600067noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-8271129968251764022010-05-11T19:52:42.540+05:302010-05-11T19:52:42.540+05:30I'm really confused about your construct ...
...I'm really confused about your construct ...<br /><br />for i in 0 to 15 loop<br />[...]<br />q(15 downto 1) := q(14 downto 0);<br />q(0) := not r(17);<br />end loop; <br /><br />As I know you would get 16 times<br />q(15 downto 1) := q(14 downto 0);<br />q(0) := not r(17);<br />as it is synthesized as parallel copies ... <br /><br />Don't get, how you can iteratively shift your Q without clock and just with a for loop ...<br /><br />I would be very interested about helping me out with this ...<br /><br />Best regards<br />ThomasUnknownhttps://www.blogger.com/profile/16317435972409935866noreply@blogger.comtag:blogger.com,1999:blog-2050962176404305705.post-44668629744593571642010-04-02T22:25:25.687+05:302010-04-02T22:25:25.687+05:30Hye GURU!!! I'm a beginner in VHDL. i have a c...Hye GURU!!! I'm a beginner in VHDL. i have a coding for square root operation. i key in data for D and the answer appears in square root. so half of my job i done.. but the prob is, i need to interface with a keypad (to key in input for D) and display at LCD (output). somethng like a calculator.. can u help me with the VHDL code.. i'm using a 3x3 keypad and spartan 3 starter kit LCD. Help me plizz!!! thnks =)Unknownhttps://www.blogger.com/profile/05299275462343783007noreply@blogger.com