Check out the below code. It is just a testbench plus design code for full adder. As you can see we have 3 input bits and we apply all the 8 combinations of inputs with a 1 ns delay between them. For applying this delay we use the "wait for" statement. This is supported by VHDL.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb IS
END tb;
ARCHITECTURE behavior OF tb IS
--Inputs
signal bit1 : std_logic := '0';
signal bit2 : std_logic := '0';
signal bit3 : std_logic := '0';
--Outputs
signal sum : std_logic;
signal carry : std_logic;
BEGIN
--Gates
gate_inst : process
begin
sum <= bit1 xor bit2 xor bit3;
carry <= (bit1 and bit2) or (bit3 and bit2) or (bit1 and bit3);
wait for 1 ns;
end process;
-- Stimulus process
stim_proc: process
begin
bit1<='0'; bit2<='0'; bit3<='0'; wait for 1 ns;
bit1<='0'; bit2<='0'; bit3<='1'; wait for 1 ns;
bit1<='0'; bit2<='1'; bit3<='0'; wait for 1 ns;
bit1<='0'; bit2<='1'; bit3<='1'; wait for 1 ns;
bit1<='1'; bit2<='0'; bit3<='0'; wait for 1 ns;
bit1<='1'; bit2<='0'; bit3<='1'; wait for 1 ns;
bit1<='1'; bit2<='1'; bit3<='0'; wait for 1 ns;
bit1<='1'; bit2<='1'; bit3<='1'; wait for 1 ns;
wait;
end process;
END;
USE ieee.std_logic_1164.ALL;
ENTITY tb IS
END tb;
ARCHITECTURE behavior OF tb IS
--Inputs
signal bit1 : std_logic := '0';
signal bit2 : std_logic := '0';
signal bit3 : std_logic := '0';
--Outputs
signal sum : std_logic;
signal carry : std_logic;
BEGIN
--Gates
gate_inst : process
begin
sum <= bit1 xor bit2 xor bit3;
carry <= (bit1 and bit2) or (bit3 and bit2) or (bit1 and bit3);
wait for 1 ns;
end process;
-- Stimulus process
stim_proc: process
begin
bit1<='0'; bit2<='0'; bit3<='0'; wait for 1 ns;
bit1<='0'; bit2<='0'; bit3<='1'; wait for 1 ns;
bit1<='0'; bit2<='1'; bit3<='0'; wait for 1 ns;
bit1<='0'; bit2<='1'; bit3<='1'; wait for 1 ns;
bit1<='1'; bit2<='0'; bit3<='0'; wait for 1 ns;
bit1<='1'; bit2<='0'; bit3<='1'; wait for 1 ns;
bit1<='1'; bit2<='1'; bit3<='0'; wait for 1 ns;
bit1<='1'; bit2<='1'; bit3<='1'; wait for 1 ns;
wait;
end process;
END;
Now when you synthesize this code you will get the above mentioned error. This is just because of the simple fact that all VHDL codes which are syntactically right are need not synthesisable. Synthesis is the process of converting the logic described by your code in terms of actual digital circuit components.A statement like "wait for 1 ns" cannot be described in terms of real hardware and hence it is not synthesisable.
You may ask why then such a keyword is available if it is not synthesisable.The reason is that there are plenty of situations where you just want to simulate( use the simulation software in your PC for verification, not running it in real FPGA hardware) the design. In those situations "wait for" statement is very useful, especially in case of testbench codes.
Also, sometimes when you add a new source in Xilinx ISE ( i think versions after 12.1) its default property "View Association" is set as "Implementation".This makes the file invisible in the "simulation" mode in ISE. Once you change this "View association" to "All" the file will be visible under all the views. For this right click on the file name in Xilinx ISE window and click on "source properties". You can see the "View Association" option now. Now do "Behavioral Check syntax" under the "Simulation" view. The errors must have gone now.
I hope the things are clear now.
i have three states in a state machine and in each state the counter counts upto 32,in each state some operations are performed.for the first state the outputs are correct but during the last countvalue the output remains for only one clock cycle whereas it should remain for two clock cycles as in previous count values.how to extend the output for two clock cycles?
ReplyDeleteOn synthesizing the test bench code by proceeding with the above given suggestions,i am still not able to rectify the error "wait for statement unsupported".Please provide me the suggestions to overcome it.
ReplyDelete