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Thursday, February 25, 2010

Arrays and Records in VHDL

In many situations you may have to use a 2-D array in your design.A 2-D array can be declared in two ways in VHDL.I will show examples:

1)Using the keyword "array".  
--first example
type array_type1 is array (0 to 3) of integer; --first define the type of array.
signal array_name1 : array_type1;  --array_name1 is a 4 element array of integers.
--second example
 --first define the type of array.
type array_type2 is array (0 to 3) of std_logic_vector(11 downto 0); 
signal array_name2 : array_type2;   --array_name2 is a 4 element array of 12-bit vectors.

2)Array of different kind of elements.
        Using array ,you can easily create an  array of similar types.But what will you do if you want an array of different type of elements,like the structures in C programming.For handling such data types there is another keyword available in VHDL-"record".
--third example
type record_name is
     a : std_logic_vector(11 downto 0);
     b: std_logic_vector(2 downto 0);
     c : std_logic;
  end record;
type array_type3 is array (0 to 3) of record_name; --first define the type of array.
signal actual_name : array_type3;
     After going through the above examples you must have got an idea about array and record declarations.Now we will see how to access them from the program.
 If the array name is "var_name" then the individual elements can be accessed by the following notation : var_name(0),var_name(1) etc....

--an example
signal test1 : std_logic_vector(11 downto 0);
test1 <= array_type2(0);
signal test2 : integer;
test2 <= array_type1(2);
--accessing the record.
a1 : std_logic_vector(11 downto 0);
b1: std_logic_vector(2 downto 0);
c1 : std_logic;
a1 <= actual_name(1).a;
b1 <= actual_name(1).b;
c1 <= actual_name(1).c;
actual_name(2).a <= "100011100011";
actual_name(1) <= (a =>  "100011100011", b => "101", c => '1');
actual_name(0) <= ("100011100011","101",'1');
Sometimes you may need to initialize a large array to zeros.If the array is very large then it is tedious to initialize it using the above methods.A keyword called "others" is used in such cases.

--an example illustrating the usage of "others".
signal test4 : std_logic_vector(127downto 0) :=  (others =>'0');
--test5 ="00000010";
signal test5 : std_logic_vector(7 downto 0) := (1 =>'1', (others =>'0') );
--initializing a 4 element array of 12 bit elements to zero.
array_name2 <= (others=> (others=>'0'));

--A 2-d array declaration
type array_type2 is array (0 to 3) of std_logic_vector(11 downto 0);
type array_type4 is array (0 to 2) of array_type2;
signal array_name4 : array_type4;  --array_name4 is a 3*4 two dimensional array.
--initialization to zeros.

Hope this small tutorial really helped you.


  1. VHDL keywords are shown in blue colour for easily differentiating.

  2. hi how to initialize an integer array to zero.

  3. type example is array (0 to 2) of integer;
    signal xx : example :=(0,0);
    xx <= (others => 0);

    1. @vipin
      It's confusing....
      The array has three integers, and you put signal xx : example :=(0,0);
      I ask to you.... It should be written as:
      signal xx : example :=(0,0,0);
      Cause the array has three integers?

  4. This is great. Thanks man. I appreciate it. arrays in vhdl are so confusing . this really helps!!!!

  5. you can also use "array (natural range <>) of" to allow the user to specify a size. I suggest looking at XST's style guide for more examples.

  6. thank u so much for the explanations with example... really useful!!

  7. i have tried array_type2,just copy thes lines

    type array_type2 is array (0 to 3) of std_logic_vector(11 downto 0);
    signal array_name2 : array_type2;
    test1 <= array_type2(0);

    but very streang ise 10.1 saying
    "The expression can not be converted to type array_type2."

    how is it possible???????

  8. @rourab : its not strange. You have written "test1 <= array_type2(0)" which should be actually "test1 <= array_name2(0)".
    Use the signal name on the RHS, not the array type.

    IF the error still comes make sure that test1 is declared as std_logic_vector(11 downto 0).

  9. To initialise the whole array of record to zero is there any easy statement like "others"? else should it be initialized individually?

  10. why did you use 2 others to initialize a 4 element array of 12 bit elements to zero.
    array_name2 <= (others=> (others=>'0'));

    why not array_name2 <= (others=> '0');

  11. @aze: i used two "others" because its a 2 dimensional array.

  12. Hi,

    I dont know how to find the number of rows and colums of a 2d array.

    For example:
    type my_2d is array(4 downto 0,6 downto 0)std_logic_vector(7 downto 0);

    variable eg_2d : my_2d;

    is there a way to find dynamically the number of rows and colums..
    row := eg_2d'ROW..

    Plz suggest.

  13. Hi,

    Could we define a type using some values of the generic? Could we use this type in the ports of the same/other block? Any way around for the second question?

    EXAMPLE (just to show the idea):
    entity stream_TEST is
    NBR_STREAM: integer := 16;
    NBIT_STREAM : integer := 10
    stream1 : in STREAM;
    stream2 : out STREAM

    Type STREAM is array(NBR_STREAM downto 0) of std_logic_vector(NBIT_STREAM downto 0);


  14. how to declare and initialize an array of 10 elements each of 32bits in size in VHDL...

  15. @harish

    type type_name is array(9 downto 0) of std_logic_vector(31 downto 0);
    signal sig_name : type_name;


    type WORD is array(31 downto 0) of std_logic;
    type type_name is array(9 downto 0) of WORD;
    signal sig_name :type_name;

  16. can we initialize the array with the elements declared in the entity like, in my case i hv declared elements (arr0,arr1,arr2,arr3,arr4,arr5,arr6,arr7,arr8,arr9) with bit_vector(31 downto 0) in entity..

    type type_name is array(9 downto 0) of std_logic_vector(31 downto 0);
    signal sig_name : type_name:=(arr0,arr1,arr2,arr3,arr4,arr5,arr6,arr7,arr8,arr9);

    1. hi i search a solution for this problem,
      I try to connect my entries to the table so that its content varies depending on the input.
      DO you found the solution

  17. Why not just use:

    Architecture behavior of testbench is
    signal INPUT : std_logic_vector (19 downto 0) := "00000000000000000000";


  18. Excuse me,

    The arrays on VHDL can has dimensions beyond 2D?
    For example, I can define a new tipe with a 5D array.

    Thanks a lot.

  19. Hi

    how to read values from an array and send them to a given port when the clock is toggling.

    please reply.

    Thank u

  20. how to make the sum of each column of a table of dimension 2, and put the money into a 1D array ???

    DO you found the solution?


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