Contact me for VHDL or Verilog projects and assignments


I have included here some of the basic doubts one may have when they start learning VHDL.I will update this list frequently.

1)If my design works perfectly in simulation level ,then does it mean that it will get synthesized?
      No.Simulation is just a way to test your design.If your design works and gives correct outputs at simulation level then you can go for synthesize. Only a subset of VHDL language can be used in synthesizable code.

2)Is "Real" data type synthesizable?
     No."real" is not synthesizable.You have to write your own customized code for dealing with real types.

3)I have written VHDL code for my design.How do I test it?
     You need to write a testbench code for testing your design.For how to write a test bench program visit here.

4)I have written a package for my design contain all the type definitions and functions that I have used.But how do I add my package to the program?
     Copy the package file and paste it in the project directory where all your other design files are stored.Now add the following line in your modules ( .vhd files) .
library work;
use work.pkg_name.all;        --pkg_name is the name of your package.
   Add these two lines after the standard library declaration in the starting of the program.If you are still unable compile the progam see this link for more information on packages.

5)While accessing an array can I give the array index as a variable?
    Yes ,you can.Array index can be a variable,but you need to remember that the range of variable should be limited such that it doesn't access outside the array limits.Otherwise a simulation error will occur.

6)What is VHDL?
    VHDL stands for VHSIC Hardware Description Language, where VHSIC stands for Very High Speed integrated Circuit.It is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits.

7)How to comment multiple lines in Xilinx ISE at a stretch?
    Select all the lines which you want to comment. Press "Alt + C" on your keyboard together. Now if you want to uncomment a group of lines just select them and press "Alt + Shift + C" together. 

8) Can you list the IEEE standard libraries available for VHDL?
    There are three libraries available as of now which are also widely supported by the synthesis tools.They are:
    a) std_logic_1164.
    b) numeric_std.
    c) numeric_bit .
   Remember that the following libraries are not IEEE standards even though they are widely used
    a) std_logic_arith .
    b) std_logic_unsigned .
  To get more information about this click here.

9)I want to know more about REAL data type. What can I do with it?
   See this post.

10)Is it possible to convert matlab or C codes to VHDL.
  There is no software tool available for converting C or matlab codes to VHDL. But with enough knowledge of VHDL basics we can write the equivalent vhdl code. For this we have to obtain the pseudo code for all the built in matlab functions used in the matlab code. There are no built in library in VHDL, like in Matlab. You can contact me for any specific query related with this.

11)I am a newbie in VHDL.Where do I start?
   First of take any vhdl book or online resource and read the vhdl syntax. I am not asking you to go in depth, but just enough so that you should be able to tell whether a piece of word in a code is a keyword or not. After that read and understand some of the simple programs given in this site. You can go through these : 1, 2, 3, 4, 5 and so on...

Note :- All the programs given in this website are tested and simulated in Xilinx ISE 10.1 unless mentioned otherwise.If you are using an older version of the program or using another simulation software then the results may slightly vary. Also the codes follow VHDL-93 standard unless otherwise mentioned.  

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