library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity crc32_8 is

port ( clk : in std_logic;

data_in : in std_logic_vector(31 downto 0);

crcout : out std_logic_vector(7 downto 0)

);

end crc32_8;

architecture Behavioral of crc32_8 is

signal crc_temp : std_logic_vector(7 downto 0) := "00000000";

signal counter1 : std_logic_vector(5 downto 0):="000000";

signal dtemp : std_logic_vector(31 downto 0):=(others => '0');

begin

dtemp <= data_in;

process(data_in,clk)

begin

if(data_in /= "00000000000000000000000000000000") then

if(clk'event and clk='1') then

--CRC calculation. Function used is : X^8 + X^2 + X^1 +1.

--Edit the next 8 lines to compute a different CRC function.

crc_temp(0) <= data_in(31-conv_integer(counter1(4 downto 0))) xor crc_temp(7);

crc_temp(1) <= data_in(31-conv_integer(counter1(4 downto 0))) xor crc_temp(7) xor crc_temp(0);

crc_temp(2) <= data_in(31-conv_integer(counter1(4 downto 0))) xor crc_temp(7) xor crc_temp(1);

crc_temp(3) <= crc_temp(2);

crc_temp(4) <= crc_temp(3);

crc_temp(5) <= crc_temp(4);

crc_temp(6) <= crc_temp(5);

crc_temp(7) <= crc_temp(6);

--CRC calculation is finished here.

--counter increment.

counter1 <= counter1 + '1';

end if;

if(counter1 ="100000") then --counter for doing the CRC operation for 8 times.

crcout <= crc_temp;

crc_temp <="00000000";

counter1 <= "000000";

else

crcout <= "00000000"; --CRC output is zero during idle time.

end if;

else

--CRC output is zero when input is not given or input is zero

crcout <= "00000000";

crc_temp <="00000000";

counter1 <= "000000";

end if;

end process;

end Behavioral;

When the input is zero or not given the output stays at zero.This module can be edited to calculate other CRC functions and for different input lengths.If you require program for a different CRC function leave a comment here.I will try to post the code as soon as possible.

why the output is zero even i already put in the input?

ReplyDeleteI have tested this code in Xilinx ISE 10.1. It worked successfully. Please check your simulation and testbench code.

ReplyDeletesorry, i am new in vhdl. i ran this code in quartus 9.0. i set the all the input to HIGH (1). however, the output is all zero.

ReplyDeleteIf you use all the inputs as '1' then I think the output is supposed to be '0'.

ReplyDeleteFirst calculate the output manually and then check it with the code.

I will give it a try. Because initially, I set the input randomly but the output is "0". So i thought of setting all the input to "1"

ReplyDeleteHey dude, i need to generate CRC-16 using X^16 + X^12 + X^5 +1 as my generator polynomial. Initial value of FFFFh and residue of F0B8h. This is according to ISO13239 standard.

ReplyDeleteThanks

hi everyone , thanks for the code, but my input is a std_logic_vector(14023 downto 0) how can adapt this code ?? thanks for answer :)

ReplyDeletehi,

ReplyDeleteI need the testbench n codin 4 crc32.. plz help me

can anyone post a 64bit CRC for 64 bit input data

ReplyDeletecan anyone post crc 16 bit code indivisually for transmitter and receiver.

ReplyDeletehow can we know that the output has no error ?? i mean how can we show whether there is any error or not

ReplyDeletewhat should be the clk value in test bench code for crc32...i m still gettin output 0 even after some random input.

ReplyDeleteplease post the code for 4 bit and 8 bit data input

ReplyDeleteif I have to design CRC, 18- bit data in, and the CRC value output is 6-bit. if i have the remainder is 111001 AS X^5 + X^4 + X^3 + 1

ReplyDeleteand the data stream as a test input (LSB on left)

could you please try to help post the change.

thank you

can u give me the code for QPSK modulation

ReplyDelete