VLSI Interview Questions - Part 1

     Here are some common interview questions asked by some VLSI companies. Try to learn the concept used in solving the questions rather than blindly going through the answers. If you have any doubts drop me a note in the comment section.

1) Design a full adder using halfadders.

Ans :

2) Find the value of A,B,C in the following circuit, after 3 clock cycles.  (ST Microelectronics)

This is a simple Ring counter. An n-bit ring counter has n states. The 3-bit counter shown above has 3 states and they are : 100 , 010 , 001 , 100 and so on..

So after 3 clock cycles  A,B,C = 100.

3) Design XOR gate using 2:1 MUX.    (Intel)

Ans :       

4) If A=10 and B=20, without using temporary register how can you interchange the two things?   (Intel) 

Ans :
    Perform the following operations sequentially:
         A = A xor B;
         B = A xor B;
         A = A xor B;
  Now A=20 and B=10.

5)What is the expression for 
output 'y' in the following circuit?

Ans : (In the notation I have used, A' means not(A), and AB means (A and B).

y = ( A'B'C + AB'C' + A'BC + ABC' )

  = ( A'C (B+B') + AC' (B+B') )

  = A'C + AC'

  = A xor C.

6)The input combination to find the stuck at '0' fault in the following circuit is:  (Texas Instruments)

Ans : X is always zero in the above circuit. So P is always zero whatever the value of A,B,C or D is.

To check the fault at X, make either inputs C or D zero, and A,B as '1'. So the input combination is "1101".

7)Consider a two-level memory hierarchy system M1 & M2. M1 is accessed first and on miss M2 is accessed. The access of M1 is 2 nanoseconds and the miss penalty (the time to get the data from M2 in case of a miss) is 100 nanoseconds. The probability that a valid data is found in M1 is 0.97. The average memory access time is:

Ans : This question is based on cache miss and success probability.

Average memory access time = (Time_m1 * success_prob ) + ( (Time_m1 + Time_m2) * miss_prob)

                    = ( 2* 0.97 ) + ( (2+100) * (1- 0.97) )

                    =  1.94 + 3.06 = 5 ns.

8)Interrupt latency is the time elapsed between:

a. Occurrence of an interrupt and its detection by the CPU

b. Assertion of an interrupt and the start of the associated ISR

c. Assertion of an interrupt and the completion of the associated ISR

d. Start and completion of associated ISR.

Ans : (b). ISR means Interrupt service routine.

These are only some of the questions I have seen. More questions will be up soon.