VHDL coding tips and tricks: Sawtooth wave generator in VHDL
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Friday, April 24, 2015

Sawtooth wave generator in VHDL

A sawtooth wave is a wave, which looks like, in the picture below:


Using VHDL, its possible to generate sawtooth waves of different precision and different frequencies. But in this simple code, we are using a single frequency and a 8 bit 2's complementary precision.

VHDL code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sawtooth is
port (clk : in std_logic; 
      wave_out : out std_logic_vector(7 downto 0);
      reset :in std_logic
     );
end sawtooth;

architecture Behavioral of sawtooth is

signal count : integer := 0;

begin

process(clk,reset)
begin
if(reset = '1') then
    count <= 0;
elsif(rising_edge(clk)) then
    if(count = 255) then
        count <= 0;
    else
        count <= count + 1;
    end if;
end if;
end process;

wave_out <= conv_std_logic_vector(count,8);

end Behavioral;


Testbench code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity tb_sawtooth is
end tb_sawtooth;

architecture Behavioral of tb_sawtooth is

component sawtooth is
port (clk : in std_logic; 
      wave_out : out std_logic_vector(7 downto 0);
      reset :in std_logic
     );
end component;

signal clk,reset : std_logic := '0';
signal wave_out : std_logic_vector(7 downto 0);

begin

uut : sawtooth port map(Clk,wave_out,reset);

Clk <= not Clk after 5 ns

process
begin
reset <= '1';
wait for 100 ns;
reset <= '0';
wait;
end process;

end Behavioral;


The code was simulated using modelsim. In modelsim we can view the sawtooth 8 bit signal in analog form. To do this, go to the wave window, right click on the wave output signal. Choose format and select analog(automatic). Now you can see the output wave window as shown below:



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