VHDL coding tips and tricks: November 2010

Monday, November 8, 2010

Synthesis Error : Wait for statement unsupported.

   This article is written as per the request of one of my readers who had some problem trying out the code given in this website. You may have seen this error in Xilinx ISE, "Wait for statement unsupported". And you may have wondered why the error is coming even after you are sure of writing a syntactically correct VHDL code.
  Check out the below code. It is just a testbench plus design code for full adder. As you can see we have 3 input bits and we apply all the 8 combinations of inputs with a 1 ns delay between them. For applying this delay we use the "wait for" statement. This is supported by VHDL.

USE ieee.std_logic_1164.ALL;

END tb;

   signal bit1 : std_logic := '0';
   signal bit2 : std_logic := '0';
   signal bit3 : std_logic := '0';
   signal sum : std_logic;
   signal carry : std_logic;


    gate_inst : process
        sum <= bit1 xor bit2 xor bit3;
        carry <= (bit1 and bit2) or (bit3 and bit2) or (bit1 and bit3);
        wait for 1 ns;
    end process;   
   -- Stimulus process
   stim_proc: process
        bit1<='0'; bit2<='0';  bit3<='0';  wait for 1 ns;
        bit1<='0'; bit2<='0';  bit3<='1';  wait for 1 ns;
        bit1<='0'; bit2<='1';  bit3<='0';  wait for 1 ns;
        bit1<='0'; bit2<='1';  bit3<='1';  wait for 1 ns;
        bit1<='1'; bit2<='0';  bit3<='0';  wait for 1 ns;
        bit1<='1'; bit2<='0';  bit3<='1';  wait for 1 ns;
        bit1<='1'; bit2<='1';  bit3<='0';  wait for 1 ns;
        bit1<='1'; bit2<='1';  bit3<='1';  wait for 1 ns;
   end process;


   Now when you synthesize this code you will get the above mentioned error. This is just because of  the simple fact that all VHDL codes which are syntactically right are need not synthesisable. Synthesis is the process of converting the logic described by your code in terms of actual digital circuit components.A statement like "wait for 1 ns" cannot be described in terms of real hardware and hence it is not synthesisable.
   You may ask why then such a keyword is available if it is not synthesisable.The reason is that there are plenty of situations where you just want to simulate( use the simulation software in your PC for verification, not running it in real FPGA hardware) the design. In those situations "wait for" statement is very useful, especially in case of testbench codes.
   Also, sometimes when you add a new source in Xilinx ISE ( i think versions after 12.1) its default property "View Association" is set as "Implementation".This makes the file invisible in the "simulation" mode in ISE. Once you change this "View association" to "All" the file will be visible under all the views. For this right click on the file name in Xilinx ISE window and click on "source properties". You can see the "View Association" option now. Now do "Behavioral Check syntax" under the "Simulation" view. The errors must have gone now.

I hope the things are clear now.