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Friday, March 5, 2010

Some useful VHDL data types

   I have given a list of very commonly used data types in VHDL.Some of these are very interesting and useful.

type e is (low,high,medium,very_high,very_low);
signal xs : e :=high;
if( xs = high ) then

--"downto" used for little endian notation.
--"to" used for big endian notation.
signal x : std_logic_vector (0 to 5):="110001";
x(4)<='1';  -- this will result in x="110011";
x(0)<='0';  -- this will result in x="010011";

type blahblah is
        a1 : std_logic_vector(3 downto 0);  

        a2 : std_logic_vector(2 downto 0);      
        a3 : integer;
    end record;
signal x : blahblah :=("1010","110",23);
(OR you can initialize as shown below)
x.a1 <="1010";
x.a2 <="110";
x.a3 <=23;

signal x : std_logic_vector (15 downto 0);
signal y : std_logic_vector (23 downto 0);
--This is correct.But make sure that the size of left and right hand operands(x and y) are same.
x(8 downto 3) <= y(19 downto 14);

 --"Range" is used for specifying the range of data types.
type day is Range 1 to 31;
type volt isRange 12 downto -12;
--declaring the object "in_volts".The range of the signal is a subset of the full range of "volt" type.
signal in_volts : volt Range 5 downto -5;

--The below type is not synthesizable,but can be used in simulation level.
--This kind of format can be used for writing easily understandable code.
type distance is Range 0 to 10000000
  m =100 cm;
  km =100000 cm;
end units distance;
signal xs : distance;
xs <= 10 km;  --xs =1000000.

 I will update this list if I come across other data types.Hope you find this useful.

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