GENERIC's in VHDL - Construction of parametrized components

THIS BLOG POST WAS UPDATED ON 06-03-2024!

      Generics are used to add customizable properties to VHDL designs. Here are some situations where you might want to use generics.

1. Customizable Properties: An example of this would be when you want to design a RAM(Random Access Memory) or a FIFO(First In First Out) whose data width and maximum number of elements can be changed without rewriting the code in multiple places.
2. Configuration Flexibility: As a code base goes through different stages in development, lets say simulation, synthesis, board level testing etc.., the developer might want to use different configurations to make the process easier. For example, the clock frequency used for functional simulation might be different from what is available in the fpga board. Instead of making multiple versions of the code, generics can be used to add multiple options in a single code base. 
3. Platform Portability: There are different FPGA vendors and devices out there, each with their unique features. To create an efficient design, the developer might need to use specific features available in fpga's. But that means one would need to write several versions of codes to target multiple fpga's. Using generics would solve such a problem.
4. Easier Hierarchical Design: Generic's can be passed down from top module to sub modules. This means that by changing specifications at the top level, you can make the changes reflect in lower-level modules as well.

    In essence, generics in VHDL allows you to create designs that are adaptable and reusable.

Example: piso.vhd

--Parallel in serial out shift register

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

--The top module has two instantiations- a 8 bit PISO(parallel in serial out) register and a 4 bit PISO.
--Without the use of generics these two components need a seperate .vhd  file.
--But I have used "generic" keyword to solve this problem.
entity piso is
    generic ( WIDTH : integer := 8 );   --default value is 8
    port(clk : in std_logic;
	 load : in std_logic;
	 in1 : in std_logic_vector(WIDTH-1 downto 0);  -- note how the size of 'in1' is not fixed.
         out1 : out std_logic
    );
end piso;

architecture Behavioral of piso is

-- note how the size of 'temp' is not fixed.
signal temp: std_logic_vector (WIDTH-1 downto 0) := (others => '0');  --initialize to zero

begin

process(clk)
begin
    if (rising_edge(clk)) then
        if (load = '0') then  -- load the register. 'load' signal is active HIGH and synchronous.
            temp <= in1;
            out1 <= '0';
        else
            --shift the register elements and output a single bit.
            out1 <= temp(WIDTH-1);
            temp(WIDTH-1 downto 1) <= temp(WIDTH-2 downto 0);
        end if;
    end if;
end process;

end Behavioral;

    In the VHDL code above, we've left the size of the PISO (Parallel-In, Serial-Out) register open-ended. This flexibility allows us to easily adjust the size of the PISO register by simply modifying the value of the generic variable WIDTH. Remarkably, no other alterations in the code are necessary. 

    Let's delve into the testbench code to witness how this adaptability is implemented in practice.

Testbench - How do you instantiate a component with generic variables:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

--Now the instantiation of this component in top module is shown below:
entity tb_piso is
end tb_piso;

architecture behavior of tb_piso is

component piso
    generic ( WIDTH : integer := 8 );   --default value is 7
    port(clk : in std_logic;
	 load : in std_logic;
	 in1 : in std_logic_vector(WIDTH-1 downto 0);  -- note how the size of 'in1' is not fixed.
	 out1 : out std_logic
    );
end component;

--signal declarations
signal in1 : std_logic_vector(7 downto 0):="10000110";
signal in2 : std_logic_vector(3 downto 0):="1001";
signal load1,load2,o1,o2 : std_logic :='0';
signal clk : std_logic := '0';

begin

--Note down the next two lines.
--This is how you pass generic parameters to the instantiated components.
--At compile time, the variable 'width' will be replaced everywhere by the values passed through here.
--Note that I used positional association for port mapping here. This is not recommended.
--Please use named association in your actual designs.

piso1 : piso generic map (WIDTH => 8) port map(clk,load1,in1,o1);
piso2 : piso generic map (WIDTH => 4) port map(clk,load2,in2,o2);

end behavior;

A very cool way to get things done, isn't it?

    Generics are perfectly synthesisable. During compilation, all generic variables are substituted with their assigned hard-coded values, ensuring smooth integration into the final design.