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Tuesday, April 13, 2010

Process sensitivity list Vs Synthesis-ability

For some of you this is a common error while synthesisng the code :
"One or more signals are missing in the process sensitivity list". In this article I will explain if there is any relation between the process sensitivity list and synthesis results.

Let us take an example.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity blog1 is
port( a,b : in unsigned(3 downto 0);
        c,d : out unsigned(3 downto 0);
        clk : in std_logic;
        rst : in std_logic
      );    
end blog1;

architecture Behavioral of blog1 is

BEGIN
--Synchronous process(some flipflop's are used for implementation)
process(clk,rst)    
begin
    if(rst = '1') then
        c<="0000";
    elsif(rising_edge(clk)) then
        c<=a;
    end if;
end process;
--combinational process(some LUT's are used for implementation)
process(a,b)
begin
    d <= a and b;
end process;

end Behavioral;

The testbench code used for testing the functionality of the code is given below:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY tb IS
END tb;

ARCHITECTURE behavior OF tb IS
   --Inputs
   signal a : unsigned(3 downto 0) := (others => '0');
   signal b : unsigned(3 downto 0) := (others => '0');
   signal clk : std_logic := '0';
   signal rst : std_logic := '0';
    --Outputs
   signal c : unsigned(3 downto 0);
   signal d : unsigned(3 downto 0);
   -- Clock period definitions
   constant clk_period : time := 10 ns;
   
BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: entity work.blog1 PORT MAP (
          a => a,
          b => b,
          c => c,
          d => d,
          clk => clk,
          rst => rst
        );
   -- Clock process definitions
   clk_process :process
   begin
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
   end process;
   -- Stimulus process
   stim_proc: process
   begin       
      b<="1111";
        a<="1001";
        wait for 20 ns;
        a<="1010";
        rst<='1';
        wait for 30 ns;
        rst<='0';
        a<="1011";
      wait;
   end process;

END;

We will first check the simulation results for the above code.See the below image:
Ok. So the code is working well as per the simulation results. Now let us synthesis the code using Xilinx ISE. Synthesis process also finished successfully.For your future reference make a copy of the synthesis report somewhere.

Now let us make a small change in the process sensitivity list of the above code.
Use process(rst)  instead of process(clk,rst).
Also use process(b) instead of process(a,b).
Simulate the design once more using the same testbench code. I am giving the waveform I got below:
What did you notice between the new waveform and old waveform. Since we have removed the "clk" and "a" from the process sensitivity lists the output signals stopped changing with respect to changes in inputs.So effectively the code is not working in the simulation.That is a big problem. But is this change going to be reflected in the synthesis results also?

Let us synthesis the new design and see.We got the following warning after synthesis:
"One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:".

Compare the new and old synthesis reports to check whether this warning has any effect on the synthesis results. To your surprise you will see that there is no change in both the reports.Both the codes have resulted in the same synthesis result.

So what about the warning? After going through some of the forums I found the folowing reasons:
1) Usually the behavior in the equations inside a process is what is intended, the sensitivity list is just a
     bookkeeping chore.It doesnt have anything to do with synthesis.
2) Technically what XST(Xilinx synthesis tool) have implemented is not what your VHDL code says to do as per the VHDL language definition. They are taking somewhat of a guess about what you really intended to do.By violating the language specification they implement it the way they think you 'really' want it and kick out a warning to let you know that the actual implementation will operate differently than your simulation shows.
           (Thanks to KJ)

Conclusion :- Sensitivity list has nothing to do with synthesis.But without the proper sensitivity list, the process will not work in simulation.So as a good practice include all the signals which are read inside the process, in the sensitivity result. The results may be varied if you are using some other tool.I have used Xilinx ISE 12.1 version for the analysis.

5 comments:

  1. A small note :- In spite of the fact that it does not give any errors it is not advisable to follow this practice.Mentioning signals in the process sensitivity list will ensure that the logic is clearly defined for the process.Also this will increase the readability of the program.

    ReplyDelete
  2. Do we need to include 'a 'in the sensitive list like this: process(clk,r,a)? Becasue the value of a is assigned to b

    if(rising_edge(clk)) then
    b<=a;

    ReplyDelete
  3. @zhensofa : no, no need to include.if you are getting any warnings in this case then you can ignore them.

    ReplyDelete
  4. Also remember that for a clocked process you may need not include the signals in the process sensitivity list, which are read at the clock edge.

    ReplyDelete
  5. This synthesis behavior stands in contradiction to the book "Top-Down Digital VLSI Design" by Hubert Kaeslin. He says that omitting a signal in the sensitivity list implies memory and therefore sequential behavior in synthesis. Since all non-sensitive signals needs to be captured in a past state. Maybe this is synthesizer dependent?

    ReplyDelete

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