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Monday, June 14, 2010

How to use Core generator to build IP cores?

 
     The CORE Generator is a design tool that delivers parameterized Intellectual Property (IP) designs optimized for Xilinx FPGAs.The CORE Generator provides ready-made functions which includes the following:
-FIFOs and memories
-Communication IP's
-IIR and FIR filters
-FFTs
-Standard bus interfaces such as PCI and PCI-X,
-Connectivity and networking interfaces (Ethernet, SPI-4.2, RapidIO, CAN and PCI Express)

  IP cores supporting many basic functions are included with the CORE Generator software and do not require a license key. More complex system level cores require purchase and installation of an additional license key.
The below image shows the core generator GUI.

In the image the numbers indicates the different parts of the interface.
1-Title Bar
2-Menu Bar
3-IP Selection Window
4-Toolbar
5-Information Window
6-Transcript Window
7-Status Bar

Let us learn how to generate an IP, in core generator.For example take the simplest IP, comparator.As per the datasheet, The comparator is used to create comparison logic that performs many functions such as A = B, A < B, A <=B  etc. A and B are external ports of up to 256 bits wide and B can optionally be set to a constant value.There many other options available. Refer to data sheet for more.

Follow the steps for generating an IP core:
1)Go to Menu bar and select File -> New project.Type in the project name and select the device you want the IP core to be generated along with other options.
2)Once the project is created click on "View by Function" to get the above shown type of image.
3)Then click on basic elements category in the IP selection window.
4)Select comparators,then double click on "comparator".In the image shown above I have comparator version 9.0.You may have a higher or lower version.But that doesnt make much difference.
5)The Comparator IP page where you can change the settings of the IP will look like this:

Type the component name as "mycomparator".In the example we want to check whether a signed signal "a" is less than "b".The width(size) of the signal is 20 bits.Select Non-registered output.To know the detailed explanation of these settings click on "View Data sheet".Click on Next to go to page 2.
6)Leave the settings on this page as such and click on Finish button.The software will now generate the core as shown in the below image.

7)The following files will be generated for 'mycomparator' in the specified directory:
mycomparator.ngc:
   Binary Xilinx implementation netlist file containing the information required to implement the module in a Xilinx (R) FPGA.
mycomparator.vhd:
   VHDL wrapper file provided to support functional simulation. This file contains simulation model customization data that is passed to a parameterized simulation model for the core.
mycomparator.vho:
   VHO template file containing code that can be used as a model for instantiating a CORE Generator module in a VHDL design.
mycomparator.xco:(this is the file to be added to your main project)
   CORE Generator input file containing the parameters used to regenerate a core.
mycomparator_xmdf.tcl:
   ISE Project Navigator interface file. ISE uses this file to determine how the files output by CORE Generator for the core can be integrated into your ISE project.
mycomparator_c_compare_v9_0_xst_1.ngc_xst.xrpt,mycomparator_flist.txt,mycomparator_readme.txt etc.

8)Now let us see how you can use this core in your main design code.
Suppose I have a vhdl code where i want to use this 20 bit comparator as a component.Then what you have to do is, open the generated vhd file by core generator and copy the below type content.
port (
a: IN std_logic_VECTOR(19 downto 0);
b: IN std_logic_VECTOR(19 downto 0);
a_lt_b: OUT std_logic);

We need the port declaration for instantiating comparator.Add these lines to the main code as shown like this:
component mycomparator
port (
a: IN std_logic_VECTOR(19 downto 0);
b: IN std_logic_VECTOR(19 downto 0);
a_lt_b: OUT std_logic);
end component;

9)Now right click on the Xilinx ISE project in Xilinx Window and click on Add source file.Select the "mycomparator.xco" file generated before.
10)Now run the code as usual.

Note :- This is just an example of how to use Core generator in general.The actual settings of different IP's may be very much different and I recommend you to go through the data sheet for specific functionalities.For any doubt contact me.
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