VHDL: Reading and Writing Real Numbers From a File

    If you want to test your VHDL design with a large number of inputs, then its not efficient or reader-friendly to put all the inputs directly into your testbench code. One option is to store the inputs in a text file and let the testbench read the contents of it as needed. Similarly it makes sense to write the outputs of your design to a file, which can be read with another software, lets say Matlab, for verification. 

      There are lot of ways in which this can be done. Each project probably requires a different approach. In this example, I have one file 1.txt where few real real numbers are saved. The example code reads each line from the input file(1.txt), extracts the real number from the read line and writes to another file, 2.txt, in a specific format.

Let me share the VHDL code for this.

Reading and writing real numbers from a file:

--include this library for file handling in VHDL.
library std;
use std.textio.all;  

--entity declaration
entity filehandle is
end filehandle;

--architecture definition
architecture Behavioral of filehandle is

--data read from the 1.txt file.
signal dataread : real;

begin

--file read and write process
read_write : process
    file read_file : text is in  "1.txt";   --declare input file
    file write_file : text is out  "2.txt";   --declare output file
    variable read_line, write_line : line; --'line' declarations
    variable data_read1 : real;
begin
    --as long as there is a line to read from the file, we will read one line
    --from 1.txt and write to file 2.txt as per the specified format.
    if (not endfile(read_file)) then   --checking the "END OF FILE" is not reached.
        --reading a line from the file and putting it in a variable 'read_line'.
        readline(read_file, read_line);
        --reading the data from the line and putting it a variable 'data_read'.
        read(read_line, data_read1);
        --assign to a signal so as we can see it in the simulation waveform
        dataread <= data_read1;   

        --write a 'line' to the variable 'write_line'. Function format is as follows:
        --write(linenumber,value(real type),justified(side),field(width),digits(natural));
        write(write_line, data_read1, right, 16, 4);
        write(write_line, data_read1, right, 16, 8);
        --write line to external file pointed by 'write_file'.
        writeline(write_file, write_line);
        write(write_line, data_read1, left, 16, 4);
        write(write_line, data_read1, left, 16, 8);
        --write line to external file pointed by 'write_file'.
        writeline(write_file, write_line);
    else
        wait;  --end of testing.
    end if;
    wait for 10 ns;
end process read_write;

end Behavioral;

Contents of the Files:

The contents of files 1.txt and 2.txt are shown below. The format of the text files are also indicated in the image. 

To simulate the code in modelsim or any other tool, simply create a file named 1.txt with the following contents in it, in the same directory as the VHDL code.

1.0

2.3

4.5

6.5

8.0

How does this work?

    After reading each line from the text file, I write two lines into the output file. First line is in right justified and second one is in left justified format. How many places need to placed after the decimal point is specified by the last argument in the write function. The total width of each number is specified by the second last argument. 

    endfile() is a function which is used to check whether the end of the file is reached. It returns a '1' when the end of a file is reached while reading.

    The data from the file cannot be read directly into a signal. That is why I have first read it into a variable and then assigned it to a signal. This helps us to see the values in the simulation waveform.

The textio.vhd package offers the following data types:

type LINE is access STRING;  -- A LINE is a pointer to a STRING value
type TEXT is file of STRING; -- A file of variable-length ASCII records.
type SIDE is (RIGHT, LEFT);   -- For justifying output data within fields.
subtype WIDTH is NATURAL;     -- For specifying widths of  output fields.

    textio also offers a large number of functions to read or write to a file. You can see the list of all available functions and the arguments used here.

Note :- One advantage of file handling in VHDL is that, you can test a large number of input combinations for checking the integrity of your design. Large number of input combinations can be automatically generated and saved into a file, and then read using the testbench.