BCD Addition - Behavioral level vhdl code

BCD or Binary coded decimal is a way of representing decimal digits in binary form. Generally 4 bits are used to represent values 0 to 9.

Decimal Digit	BCD 8 4 2 1
0	0 0 0 0
1	0 0 0 1
2	0 0 1 0
3	0 0 1 1
4	0 1 0 0
5	0 1 0 1
6	0 1 1 0
7	0 1 1 1
8	1 0 0 0
9	1 0 0 1

In this post we discuss about BCD addition. The output of a BCD adder is also supposed to be in BCD format. So after the normal binary addition of the inputs, there should be a BCD adjustment code to convert the result to BCD format.

Consider the below BCD addition :

1001 + 1000 = 10001
   9 +    8 =    17

Since the range of input is 0 to 9, the maximum output is 18. If you consider a carry it becomes 19. This means at the output side we need a 4 bit sum and a 1 bit carry to represent the MSB digit.
For multiple digit addition , you can connect the carry_out to the carry input of the next adder. A simple cascading network of these small adders is enough to realize the multiple digit BCD addition.

VHDL code for single digit BCD addition:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity bcd_adder is
    port(
        a,b  : in  unsigned(3 downto 0); -- input numbers.
        carry_in : in std_logic;
        sum  : out  unsigned(3 downto 0); 
        carry : out std_logic  
    );
end bcd_adder;

architecture arch of bcd_adder is


begin

process(a,b)
variable sum_temp : unsigned(4 downto 0);
begin
    sum_temp := ('0' & a) + ('0' & b) + ("0000" & carry_in); 
    if(sum_temp > 9) then
        carry <= '1';
        sum <= resize((sum_temp + "00110"),4);
    else
        carry <= '0';
        sum <= sum_temp(3 downto 0);
    end if; 
end process;   

end arch;

If you see the code, there are three inputs. The 4 bit BCD digits 'a' and 'b'. The carry_in comes from the carry output from the neighboring adder(in the LSB side). For the first adder(which adds the least significant digits) carry_in is '0'.

I have used the following test bench code to test the design. The code is synthesisable and have been tested using Xilinx ISE 13.1. It should work with other tools as well.

Testbench code for the BCD adder:-

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
ENTITY tb_test IS
END tb_test;
 
ARCHITECTURE behavior OF tb_test IS 

    COMPONENT bcd_adder
    PORT(
         a : IN  unsigned(3 downto 0);
         b : IN  unsigned(3 downto 0);
            carry_in : in std_logic;
         sum : OUT  unsigned(3 downto 0);
         carry : OUT  std_logic
        );
    END COMPONENT;
    
   signal a,b,sum : unsigned(3 downto 0) := (others => '0');
   signal carry,carry_in : std_logic;
 
BEGIN
 
    -- Instantiate the Unit Under Test (UUT)
   uut: bcd_adder PORT MAP (
          a => a,
          b => b,
             carry_in => carry_in,
          sum => sum,
          carry => carry
        );
          
   -- Stimulus process
   stim_proc: process
   begin        
      a <= "1001"; b <= "1001"; carry_in <= '1'; wait for 100 ns;
        a <= "1000"; b <= "1001"; wait for 100 ns;
        a <= "0101"; b <= "1001"; wait for 100 ns;
        a <= "0011"; b <= "1001"; wait for 100 ns;
        a <= "1001"; b <= "0000"; carry_in <= '0'; wait for 100 ns;
        a <= "1001"; b <= "0111"; wait for 100 ns;
        a <= "0110"; b <= "0011"; wait for 100 ns;
      wait;
   end process;

END;

Note:- I have not given the code for cascading adders. But I hope its fairly simple to do it yourself.