FPGA: Tips to Reduce Power Consumption in RAM's

    I want to discuss some points which will be helpful for reducing the power consumed in an FPGA. I will be particularly focusing on the power dissipation caused by the RAM's. These points are selected from the Xilinx white paper for Virtex-5 system power design considerations. But I will note down the points which will apply for any Xilinx FPGA.

Types of Power consumption in FPGA:

     There are two primary types of power consumption in FPGA's: static and dynamic. 

    Static power is consumed due to transistor leakage while Dynamic power is consumed by toggling nodes as a function of voltage, frequency, and capacitance. The leakage current is directly proportional to the speed of the processor, operating voltage of the processor and junction(or die) temperature. 

    So static power increases from Virtex 4 FPGA to Virtex 5 FPGA. On the other hand dynamic power reduces from Virtex 4(90 nm device) to Virtex 5(65 nm device). This is because dynamic power is directly proportional to the voltage of operation and the capacitance (this includes the transistor parasitic capacitance and metal interconnect capacitance). From Virtex 4 to Virtex 5, these two parameters decrease and so we get around 40 % reduction in dynamic power.

You can get more details from the pdf link I had shared above.

Tips to reduce power consumption:

      Xilinx has given some tips in reducing the power consumption by designing RAM's intelligently. 

1. Choose the right RAM primitive for your design.

    When choosing a RAM organization within the target architecture, the width, depth and functionality must be considered. Choosing the right memory facilitates the selection of the most power-efficient resource for the end design.

2. Ensure that, the block RAM is only enabled when data is needed from it.

    This is because the power requirements of a block RAM is directly proportional to the amount of time it is enabled. Normally for ease of coding the enable signal is always "ON". But for power sensitive applications take some extra effort to make use of enable signal of RAM.

    Another tip regarding enable signal is explained in the following example. Say you want a 2k x 8 bit RAM in your design. Then use four 512 x 8 bit RAM's for this. Now use a separate enable signal for each RAM. This needs some extra logic, but at any time only one RAM will be ON , so we can save around 75% of the power.

3. Ensure the WRITE_MODE of RAM is set properly.

    If the block RAM contents are never read during a write, the RAM power can be reduced by a significant amount with the selection of the NO_CHANGE mode rather than the default WRITE_FIRST mode. This mode can be set easily if you are using the core generator GUI to create the RAM module.

Note:- It would be wise to see the Xilinx white paper on power reduction for your particular FPGA before start the coding for your design.This will be helpful in getting useful tips which are device specific.

VHDL: LFSR Based Random Number Generator

     I want to share a synthesisable random number generator in VHDL in this post. I had previously created a LFSR(Linear feedback shift register) based random number generator. But it was faulty, as pointed out by an expert in the field, Chris, who had happen to see the code. The issue was that the tap values I had taken for feeding back the shift register was wrong. This resulted in a non-maximum length sequence. For example as Chris pointed out, in the older code, when the register size is 32 bits the sequence period is 2^21-1 and not 2^32-1 as I had claimed.

    So I have written another code which uses the correct tap values to ensure that the sequence generated is of maximum length. The project is uploaded at opencores.org and can be downloaded for free. The code take cares of register sizes from 3 bit to 168 bits. The tap values were referred from a Xilinx documentation about LFSR.

    The project can be downloaded from, Random number generator using LFSR. After downloading, extract the contents of the zip file. The codes and documentation is available in the folder named "trunk".
Currently the project is in alpha stage. Please let me know if you find any bugs in the code

Hope this project is useful.