I want to share a synthesisable random number generator in VHDL in this post. I had previously created a LFSR(Linear feedback shift register) based random number generator. But it was faulty, as pointed out by an expert in the field, Chris, who had happen to see the code. The issue was that the tap values I had taken for feeding back the shift register was wrong. This resulted in a non-maximum length sequence. For example as Chris pointed out, in the older code, when the register size is 32 bits the sequence period is 2^21-1 and not 2^32-1 as I had claimed.
So I have written another code which uses the correct tap values to ensure that the sequence generated is of maximum length. The project is uploaded at opencores.org and can be downloaded for free. The code take cares of register sizes from 3 bit to 168 bits. The tap values were referred from a Xilinx documentation about LFSR.
The project can be downloaded from, Random number generator using LFSR. After downloading, extract the contents of the zip file. The codes and documentation is available in the folder named "trunk".
Currently the project is in alpha stage. Please let me know if you find any bugs in the code
So I have written another code which uses the correct tap values to ensure that the sequence generated is of maximum length. The project is uploaded at opencores.org and can be downloaded for free. The code take cares of register sizes from 3 bit to 168 bits. The tap values were referred from a Xilinx documentation about LFSR.
The project can be downloaded from, Random number generator using LFSR. After downloading, extract the contents of the zip file. The codes and documentation is available in the folder named "trunk".
Currently the project is in alpha stage. Please let me know if you find any bugs in the code
Hope this project is useful.
This code is actually done in a fairly nice way -- at least from the perspective of the function. My biggest concern is the async load and async enables. Both can be async, which is almost always a bad idea. Async signals need VERY careful attention to avoid errors. They are particularly good at destroying state machines and control logic.
ReplyDeleteThis is because there is data and clock skew, thus each LUT+FF that uses the async signal as an input will receive each bit of the signal at a slightly different time. (or will get a clock edge at a slightly different time)
For the LFSR case, initializing to something like 0001 can cause the design to fail. If load is deasserted near a clock edge (at any clock rate), then the lsb might shift in a 0 (if load = 0 at this FF). If the upper bits still have load asserted (eg, there is a longer delay from load to these FF's), then they will stay 0's. Thus the LFSR will transition from 0001 to 0000. At this point, the LFSR is stuck.
Also, async loads are often used in interview questions as something to avoid.
@Chris: As per your comments I have modified the code a little and have uploaded the new version. Please check it out.
ReplyDeleteI have removed the input "out_enable" as it is not necessary.
Also the setting the seed functionality is made synchronous instead of asynchronous.
can u please provide me a code for binary multiplier.......
ReplyDeletethanx in advance
Mr. Vipin,
ReplyDeleteI have implemented this module in order to produce white noise as an audio source, but the frequency response I am getting is not flat.
The low end is cut off and rises inverse-exponentially to a flat PSD at around 8kHz (Fs = 44100Hz). Therefore the white noise sounds very high-pass filtered.
Do you have any idea why this is happening? I have tried with different word lengths and seed values without any luck.
Here is a link showing the PSD:
http://www.photostand.co.za/images/934h5nswi8annoh10xr.png
Thank you!
Can you please post the code in this post itself? Opencores asks for registration and confirmation takes another two or more days to complete!
ReplyDeleteThanks!
sndn_shr@yahoo.com