VHDL coding tips and tricks: Example : D Flip-Flop with Synchronous Reset,Set and Clock Enable
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Wednesday, September 8, 2010

Example : D Flip-Flop with Synchronous Reset,Set and Clock Enable

   As per the request from readers I have decided to post some basic VHDL codes for beginners in VHDL. This is the first one, a basic D Flip-Flop with Synchronous Reset,Set and Clock Enable(posedge clock).The code is self explanatory and I have added few comments for easy understanding.
--library declaration for the module.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--This is a D Flip-Flop with Synchronous Reset,Set and Clock Enable(posedge clk).
--Note that the reset input has the highest priority,Set being the next highest
--priority and clock enable having the lowest priority.
entity example_FDRSE is
   port(
      Q : out std_logic;      -- Data output
      CLK :in std_logic;      -- Clock input
      CE :in std_logic;    -- Clock enable input
      RESET :in std_logic;  -- Synchronous reset input
      D :in  std_logic;      -- Data input
      SET : in std_logic   -- Synchronous set input
   );
end example_FDRSE;
architecture Behavioral of example_FDRSE is  --architecture of the circuit.
begin  --"begin" statement for architecture.
process(CLK) --process with sensitivity list.
begin  --"begin" statment for the process.
  if ( rising_edge(CLK) ) then  --This makes the process synchronous(with clock)
    if (RESET = '1') then
         Q <= '0';
     else
           if(SET = '1') then
             Q <= '1';
           else
              if ( CE = '1') then
               Q <= D;      
             end if;
           end if;
      end if;
  end if;      
end process;  --end of process statement.
end Behavioral;
Note :- This is a flip flop which is defined in the Xilinx language template for spartan-3.If you synthesis this design it will use exactly one flip flop and some buffers alone.It will not use any LUT's for the implementation.

6 comments:

  1. @awais : I left the testbench for this module as an exercise to students. Read this post and write a similar testbench.
    http://vhdlguru.blogspot.com/2010/03/positive-edge-triggered-jk-flip-flop.html

    ReplyDelete
  2. Hi all !!
    I have a flip-flop that I need to enable for only one clock cycle. What is the standard practice for single-cycle enable signal in these kind of situations?

    ReplyDelete
  3. please write program for d ff for symmetric in reset clk and only

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  4. Clear and preset are independent of the clock signal

    ReplyDelete