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Wednesday, September 8, 2010

Example : D Flip-Flop with Asynchronous Clear,Set and Clock Enable

    As per the request from readers I have decided to post some basic VHDL codes for beginners in VHDL. This is the second one in the series, a basic D Flip-Flop with Asynchronous Clear,Set and Clock Enable(negedge clock).The code is self explanatory and I have added few comments for easy understanding.

--library declaration for the module.
library IEEE;
--This is a D Flip-Flop with Asynchronous Clear,Set and Clock Enable(negedge clock).
--Note that the clear input has the highest priority,preset being the next highest
--priority and clock enable having the lowest priority
entity example_FDCPE is
      Q : out std_logic;      -- Data output
      CLK :in std_logic;      -- Clock input
      CE :in std_logic;    -- Clock enable input
      CLR :in std_logic;  -- Asynchronous clear input
      D :in  std_logic;      -- Data input
      PRE : in std_logic   -- Asynchronous set input
end example_FDCPE;

architecture Behavioral of example_FDCPE is  --architecture of the circuit.

begin  --"begin" statement for architecture.

process(CLR,PRE,CLK) --process with sensitivity list.
begin  --"begin" statment for the process.

    if (CLR = '1') then  --Asynchronous clear input
           Q <= '0';
           if(PRE = '1') then  --Asynchronous set input
               Q <= '1';
               if ( CE = '1' and  falling_edge(CLK) ) then
                  Q <= D;      
              end if;
          end if;
   end if;

end process;  --end of process statement.

end Behavioral;

Note :- This is a flip flop which is defined in the Xilinx language template for spartan-3.If you synthesis this design it will use exactly one flip flop and some buffers alone.It will not use any LUT's for the implementation.


  1. Thank you for your wonderful post but as I am newbie in VHDL.

    How about an example of shift register that can increment, shift left , shift right ?

    Thanks again ^_^

  2. may not be exactly as per your requirement but I have written code for a PISO shift register here:

    Using this you can try to code the module you want.

  3. Can you please post a test bench that could help simulating your code?

  4. Value of q is not changing in simulation

    1. This comment has been removed by the author.


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