--library declaration for the module.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--This is a D Flip-Flop with Asynchronous Clear,Set and Clock Enable(negedge clock).
--Note that the clear input has the highest priority,preset being the next highest
--priority and clock enable having the lowest priority
entity example_FDCPE is
port(
Q : out std_logic; -- Data output
CLK :in std_logic; -- Clock input
CE :in std_logic; -- Clock enable input
CLR :in std_logic; -- Asynchronous clear input
D :in std_logic; -- Data input
PRE : in std_logic -- Asynchronous set input
);
end example_FDCPE;
architecture Behavioral of example_FDCPE is --architecture of the circuit.
begin --"begin" statement for architecture.
process(CLR,PRE,CLK) --process with sensitivity list.
begin --"begin" statment for the process.
if (CLR = '1') then --Asynchronous clear input
Q <= '0';
else
if(PRE = '1') then --Asynchronous set input
Q <= '1';
else
if ( CE = '1' and falling_edge(CLK) ) then
Q <= D;
end if;
end if;
end if;
end process; --end of process statement.
end Behavioral;
Note :- This is a flip flop which is defined in the Xilinx language template for spartan-3.If you synthesis this design it will use exactly one flip flop and some buffers alone.It will not use any LUT's for the implementation.
Thank you for your wonderful post but as I am newbie in VHDL.
ReplyDeleteHow about an example of shift register that can increment, shift left , shift right ?
Thanks again ^_^
may not be exactly as per your requirement but I have written code for a PISO shift register here:
ReplyDeletehttp://vhdlguru.blogspot.com/2010/09/examples-for-gate-level-and-behavior.html
Using this you can try to code the module you want.
Can you please post a test bench that could help simulating your code?
ReplyDeleteValue of q is not changing in simulation
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