VHDL coding tips and tricks: How to use coe file for initializing BRAM
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Sunday, October 31, 2010

How to use coe file for initializing BRAM

   I hope you have gone through my previous post about how to create a BRAM using core generator.If you are not familiar with the steps then please read it here.This post is a continuation of the above mentioned article. Normally we initialize all the memory locations in a BRAM to zero using the "Fill Remaining memory locations" option in core generator. But this article will tell you how to use coe file as an initialization vector.Follow the steps:
1)Create a BRAM of depth = 16 and read and write width = 8 bits.
2)Check the "Load Init File" under the "Memory Initialization" option. Also select the file named "bram_contents.coe".
3)Before clicking on the generate button create a new file named bram_contents.coe and paste the following contents into it:
memory_initialization_radix=10;
memory_initialization_vector=1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16;
In the above text radix means the raidx of the data. I have written decimal data in the vector so my radix is "10". If you want to give the memory contents in binary form then change the coe file like this:
memory_initialization_radix=2;
memory_initialization_vector=0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111;
4)Now click on the generate button.

Now simulate the BRAM with the following testbench code given below:

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity testbench is
end testbench;

architecture Behavioral of testbench is

--temporary signal declarations.
signal ena : std_logic := '0';
signal wea : std_logic_VECTOR(0 downto 0):="0";
signal dina,douta : std_logic_VECTOR(7 downto 0) := (others => '0');
signal addra : std_logic_VECTOR(3 downto 0) := (others => '0');
signal clk : std_logic := '0';

begin

--Instantiating BRAM.
BRAM : entity work.BRAM_test
    port map(
    clka => clk,  --clock for writing data to RAM.
    ena => ena,   --Enable signal.
    wea => wea,   --Write enable signal for Port A.
    addra => addra, --4 bit address for the RAM.
    dina => dina,   --8 bit data input to the RAM.
    douta => douta);  --8 bit data output from the RAM.

--Simulation process.
process
begin
    wait for 1 ns;
    addra <= X"0";  --reset the address value for reading from memory location "0"
    --reading all the 16 memory locations in the BRAM.
    for i in 0 to 15 loop
        ena <= '1';  --Enable RAM always.
        wea <= "0";
        wait for 2 ns;
        addra <= addra + "1";
    end loop;
    wait;
end process;  

--Clock generation - Generates 500 MHz clock with 50% duty cycle.
process
begin
    clk <= '1';
    wait for 1 ns;  --"ON" time.
    clk <= '0';
    wait for 1 ns;  --"OFF" time.
end process;  
 
end Behavioral;

The above code is used for reading the BRAM addresses from 0 to 15 which should display the contents of coe file. Check the given waveform for verification.
Note :- This is just one use of coe file.In different IP cores we can use coe file in different ways. For example coe file can be used to give the filter coefficients for FIR IP core.For testing purpose I have used Xilinx ISE 12.1 version and BRAM version 4.1. The options in the core generator tool may vary slightly depending on the version you are using.

2 comments:

  1. How to write the contents of BRAM in a text file, without using textio?

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  2. https://www.youtube.com/watch?v=zX4tZPBL9oY

    ReplyDelete