If you are someone like me, who suddenly started using the Xilinx Vivado tool after using Xilinx ISE for a long time, then you might have noticed that Vivado currently doesn't support the Automatic testbench generation.
This is such a major disappointment for many of us. But luckily there are many online tools which does more or less the same. In this Video, I used the Doulos tool for creating testbenches for my VHDL designs. Once generated I tested the codes using the latest Vivado 2019.2 version.
Hope this is useful for you. Enjoy!
library ieee;
ReplyDeleteuse ieee. std_logic_1164.all;
use ieee. std_logic_arith.all;
use ieee. std_logic_unsigned.all;
entity SR_FF is
PORT( S,R,CLOCK: in std_logic;
Q, QBAR: out std_logic);
end SR_FF;
Architecture behavioral of SR_FF is
begin
PROCESS(CLOCK)
variable tmp: std_logic;
begin
if(CLOCK='1' and CLOCK'EVENT) then
if(S='0' and R='0')then
tmp:=tmp;
elsif(S='1' and R='1')then
tmp:='Z';
elsif(S='0' and R='1')then
tmp:='0';
else
tmp:='1';
end if;
end if;
Q <= tmp;
QBAR <= not tmp;
end PROCESS;
end behavioral;
LIBRARY ieee;
ReplyDeleteUSE ieee.std_logic_1164.all;
ENTITY counter IS
PORT ( clk, rst: IN STD_LOGIC;
count: OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END counter;
ARCHITECTURE state_machine OF counter IS
TYPE state IS (zero, one, two, three, four,
five, six, seven, eight, nine);
SIGNAL pr_state, nx_state: state;
BEGIN
PROCESS (rst, clk)
BEGIN
IF (rst='1') THEN
pr_state <= zero;
ELSIF (clk'EVENT AND clk='1') THEN
pr_state <= nx_state;
END IF;
END PROCESS;
PROCESS (pr_state)
BEGIN
CASE pr_state IS
WHEN zero =>
count <= "0000";
nx_state <= one;
WHEN one =>
count <= "0001";
nx_state <= two;
WHEN two =>
count <= "0010";
nx_state <= three;
WHEN three =>
count <= "0011";
nx_state <= four;
WHEN four =>
count <= "0100";
nx_state <= five;
WHEN five =>
count <= "0101";
nx_state <= six;
WHEN six =>
count <= "0110";
nx_state <= seven;
WHEN seven =>
count <= "0111";
nx_state <= eight;
WHEN eight =>
count <= "1000";
nx_state <= nine;
WHEN nine =>
count <= "1001";
nx_state <= zero;
END CASE;
END PROCESS;
END state_machine;