VHDL coding tips and tricks: Some more clarification on "Signal changing at both clock edges" matter

Monday, January 10, 2011

Some more clarification on "Signal changing at both clock edges" matter

Sorry for not posting for a long time. Recently I received a comment on one of my old posts which answers the question Can you change a signal at both positive and negative edges of the clock.

In the above post I said that a signal cannot be changed both at positive and negative edges. Basically the code will not synthesis. After reading the post,one of my reader, Arseni posted the following comment.

This post is an answer to his question. For making it a general case I have slightly changed the code Arseni posted. Here it is:

library IEEE;

entity test is
port (A : in std_logic;
        B,D : in std_logic_vector(3 downto 0);
        C : out std_logic_vector(3 downto 0)
end test;

architecture Behavioral of test is


    if A = '1' then
        C <= B;
        C <= D;
    end if;

end Behavioral;

In the code whenever the value of signal A is '1' B is assigned to C, otherwise D is assigned to C.
As the commenter indicates the signal C is changed irrespective of the value of A(whether it is low or high) here. So why did this code synthesis properly?

Because if you closely watch you can notice that the C is changed based on the level value of the signal A. 'C' is not changed by checking whether the value of 'A' changes from 1 to 0 or 0 to 1. It is concerned with only the value(whether it is 0 or 1). That means a flip flop is not used for synthesising the behavioral code given above.

The rule a signal cannot be changed at both clock edges  is for edge triggered actions. Which means the output is through a flip flop and some kind of additional combinatorial logic.

In the code given above, the synthesis only uses some LUT-2 components. Its doesnt use any flip flops.

Note :- The code is simulated and synthesised successfully using the Xilinx ISE 12.1. But it will mostly work with other tools too.


  1. Please - stop using these libraries!


    (especially when you don't even use them!)

    Why not: http://parallelpoints.com/node/3

  2. mmm, signal D should be in the sensitivity list, otherwise when A = '0' the output C should keep their previous value, acting as a latch, which is not recommended at all. The synthesis maybe works ok, because synthesizers assume this design models a multiplexer, but this can cause simulation and synthesis mismatch.