Can you change a signal at both positive and negative edges of the clock?

    Consider the following code:

signal c : std_logic_vector(3 downto 0):="0000";
process(clk)
begin
c <= c +'1';
end process;

This code is supposed to work as a simple 4 bit counter,counting at both negative and positive edge of the clock.The design works perfectly in the simulation level.But when you synthesize this code you will get the following warnings :

WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2170 - Unit test : the following signal(s) form a combinatorial loop: Madd_c4.
WARNING:Xst:2170 - Unit test : the following signal(s) form a combinatorial loop: Madd_c6.
WARNING:Xst:2170 - Unit test : the following signal(s) form a combinatorial loop: Madd_c_cy<0>.
 Normally warnings can be neglected during synthesis.But in this case "the input clk is never used".So the basically the design will not work.It is just a combinatorial circuit with feedback.
Now if you write the code in the following way then you will get a synthesis error.
"Signal c cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release."

process(clk)
begin
if(clk'event and clk='1') then   -- for posedge
c <= c +'1';
end if;
if(clk'event and clk='0') then  --for negedge
c <= c +'1';
end if;
end process;

These code clearly shows that it is not possible to change a signal at both negative and positive edge of the clock.Xilinx ISE either synthesizes it badly or it gives an error.