VHDL code for Hexadecimal to 7-Segment Display Converter

Few years back, I wrote a post on BCD to 7-segment display converter. This code is an update to the old code. The main changes are:

• Removed the clock which was unnecessary.
• Removed the libraries which weren't used.
• Extended for accepting hexadecimal inputs, and not only BCD.

The module takes 4 bit BCD as input and outputs 7 bit decoded output for driving the seven segment display unit. A seven segment display can be used to display hexadecimal digits. They have LED or LCD elements which becomes active when the input is zero.The figure shows how different digits are displayed:

VHDL code for the 7 segment converter:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity to_7seg is
    Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);
          seg7 : out  STD_LOGIC_VECTOR (6 downto 0)
             );
end to_7seg;

architecture Behavioral of to_7seg is

begin

--'a' corresponds to MSB of seg7 and 'g' corresponds to LSB of seg7.
process (A)
BEGIN
    case A is
        when "0000"=> seg7 <="0000001";  -- '0'
        when "0001"=> seg7 <="1001111";  -- '1'
        when "0010"=> seg7 <="0010010";  -- '2'
        when "0011"=> seg7 <="0000110";  -- '3'
        when "0100"=> seg7 <="1001100";  -- '4' 
        when "0101"=> seg7 <="0100100";  -- '5'
        when "0110"=> seg7 <="0100000";  -- '6'
        when "0111"=> seg7 <="0001111";  -- '7'
        when "1000"=> seg7 <="0000000";  -- '8'
        when "1001"=> seg7 <="0000100";  -- '9'
        when "1010"=> seg7 <="0001000";  -- 'A'
        when "1011"=> seg7 <="1100000";  -- 'b'
        when "1100"=> seg7 <="0110001";  -- 'C'
        when "1101"=> seg7 <="1000010";  -- 'd'
        when "1110"=> seg7 <="0110000";  -- 'E'
        when "1111"=> seg7 <="0111000";  -- 'F'
        when others =>  NULL;
    end case;
end process;

end Behavioral;

Testbench code for the converter:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
 
ENTITY tb_seg IS
END tb_seg;
 
ARCHITECTURE behavior OF tb_seg IS 

    COMPONENT to_7seg
    PORT(
         A : IN  std_logic_vector(3 downto 0);
         seg7 : OUT  std_logic_vector(6 downto 0)
        );
    END COMPONENT;
   
   signal A : std_logic_vector(3 downto 0) := (others => '0');
   signal seg7 : std_logic_vector(6 downto 0);
 
BEGIN
 
    -- Instantiate the Unit Under Test (UUT)
   uut: to_7seg PORT MAP (
          A => A,
          seg7 => seg7
        );

  -- Stimulus process
   stim_proc: process
   begin        
        for i in 0 to 15 loop
            A <= conv_std_logic_vector(i,4);
            wait for 50 ns;
        end loop;
      wait;
   end process;

END;

Simulation waveform:

The code was synthesised and simulated using Xilinx ISE 14.6. The following waveform verifies the correct working of the code.