VHDL coding tips and tricks: 4 bit Binary to Gray code and Gray code to Binary converter in VHDL

Saturday, October 28, 2017

4 bit Binary to Gray code and Gray code to Binary converter in VHDL

Gray codes are non-weighted codes, where two successive values differ only on one bit. Through this post, I want to share two simple gate level VHDL codes for converting binary number to Gray and vice versa.

Logic circuit for 4 bit Binary to Gray code converter:


Logic circuit for 4 bit Gray code to Binary converter:


VHDL Code for Binary to Gray code conversion:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

entity bin2gray is
port(   bin : in std_logic_vector(3 downto 0);  --binary input
        G : out std_logic_vector(3 downto 0)  --gray code output
        );
end bin2gray;

architecture gate_level of bin2gray is 

begin

--xor gates.
G(3) <= bin(3);
G(2) <= bin(3) xor bin(2);
G(1) <= bin(2) xor bin(1);
G(0) <= bin(1) xor bin(0);

end;

VHDL Code for Gray code to Binary conversion:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

entity gray2bin is
port(   G : in std_logic_vector(3 downto 0);    --gray code input
        bin : out std_logic_vector(3 downto 0)  --binary output
        );
end gray2bin;

architecture gate_level of gray2bin is 

begin

--xor gates.
bin(3) <= G(3);
bin(2) <= G(3) xor G(2);
bin(1) <= G(3) xor G(2) xor G(1);
bin(0) <= G(3) xor G(2) xor G(1) xor G(0);

end;

Single Testbench for both the designs:

library ieee;
use ieee.std_logic_1164.all;
 
entity tb is
end tb;
 
architecture behavior of tb is 
 
    -- component declaration for the unit under test's (uut) 
component bin2gray is
    port(   bin : in std_logic_vector(3 downto 0);
            g : out std_logic_vector(3 downto 0)
            );
end component;

component gray2bin is
port(   g : in std_logic_vector(3 downto 0);
        bin : out std_logic_vector(3 downto 0)
        );
end component;

signal bin,g,bin_out : std_logic_vector(3 downto 0) := (others => '0');
 
begin
    -- instantiate the unit under test's (uut)
   uut1: bin2gray port map (
          bin => bin,
          g => g
        );
 
   uut2: gray2bin port map (
          g => g,
          bin => bin_out
        );
          
   -- stimulus process
   stim_proc: process
   begin        
        bin <= "0000";    wait for 10 ns;
        bin <= "0001";  wait for 10 ns;
        bin <= "0010";  wait for 10 ns;
        bin <= "0011";  wait for 10 ns;
        bin <= "0100";    wait for 10 ns;
        bin <= "0101";  wait for 10 ns;
        bin <= "0110";  wait for 10 ns;
        bin <= "0111";  wait for 10 ns;
        bin <= "1000";    wait for 10 ns;
        bin <= "1001";  wait for 10 ns;
        bin <= "1010";  wait for 10 ns;
        bin <= "1011";  wait for 10 ns;
        bin <= "1100";    wait for 10 ns;
        bin <= "1101";  wait for 10 ns;
        bin <= "1110";  wait for 10 ns;
        bin <= "1111";  wait for 10 ns;     
      wait;
   end process;

end;

Simulation Waveform:

The code was simulated using Xilinx ISE 14.6 tool. The following waveform verifies the correctness of both the designs. The output of binary to gray entity is connected as input of gray to binary converter. As you can see the bin and bin_out signals are the same. This verifies that the codes are working well.


Do you notice a pattern in how the output bits are calculated. What do you think of of an n-bit converter? For learning purposes, try implementing an n-bit version of the above designs.

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