I want to share the VHDL code for a 4-bit Ripple carry adder(

**RCA**) implemented using basic logic gates such as AND, OR, XOR etc.. The entity port has two 4-bit inputs and one 1-bit carry input. There are two outputs, a 4-bit*sum*and a 1-bit*carry.* Why is this adder called ripple carry? If you look at the block diagram below, the respective bits from the input operands are fed to the full adders. And then the carry out from each full adder is fed as the carry in of the next full adder. In a way you can say that the carry is

**rippled**from the right(least significant bit position) to the left(most significant bit position) side.__VHDL Code for 4 bit Ripple Carry Adder:__

__VHDL Code for 4 bit Ripple Carry Adder:__

--libraries to be used are specified here library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; --entity declaration with port definitions entity rc_adder is --ripple carry adder port(num1 : in unsigned(3 downto 0); --4 bit input 1 num2 : in unsigned(3 downto 0); --4 bit input 2 sum : out unsigned(3 downto 0); --4 bit sum carry : out std_logic -- carry out. ); end rc_adder; --architecture of entity architecture gate_level of rc_adder is --temporary signal declarations(for intermediate carry's). signal c0,c1,c2,c3 : std_logic := '0'; begin --first full adder sum(0) <= num1(0) xor num2(0); --sum calculation c0 <= num1(0) and num2(0); --carry calculation --second full adder sum(1) <= num1(1) xor num2(1) xor c0; c1 <= (num1(1) and num2(1)) or (num1(1) and c0) or (num2(1) and c0); --third full adder sum(2) <= num1(2) xor num2(2) xor c1; c2 <= (num1(2) and num2(2)) or (num1(2) and c1) or (num2(2) and c1); --fourth(final) full adder sum(3) <= num1(3) xor num2(3) xor c2; c3 <= (num1(3) and num2(3)) or (num1(3) and c2) or (num2(3) and c2); --final carry assignment carry <= c3; end gate_level;

__A little tip on Concurrency in VHDL:__

We have used basic logic gates here to implement the adder. This is known as Gate Level Modelling in VHDL.

All the statements in the

*architecture body*in the above code are*concurrent*, which means they execute parallelly. But since the output of one gate is connected as the input to another, they appear as concatenated and looks as if the first line executes first before the second line. If you are not convinced of what I am saying, you can change the line order as you like, and you would still get the same simulation waveform.

__Testbench code for Ripple carry adder:__

--library declarations library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; --this is how entity for your testbench code has to be declared. entity testbench is end testbench; architecture behavior of testbench is --signal declarations. signal num1,num2,sum : unsigned(3 downto 0) :=(others => '0'); signal carry : std_logic:='0'; begin --entity instantiation adder : entity work.rc_adder port map(num1 => num1, num2 => num2, sum => sum, carry => carry); --definition of simulation process stimulus : process begin --result should be sum=11 and carry=0 num1 <= to_unsigned(2,4); num2 <= to_unsigned(9,4); wait for 2 ns; --result should be sum=13 and carry=0 num1 <= to_unsigned(10,4); num2 <= to_unsigned(3,4); wait for 2 ns; --result should be sum=14 and carry=0 num1 <= to_unsigned(8,4); num2 <= to_unsigned(6,4); wait for 2 ns; --result should be sum=0 and carry=1 num1 <= to_unsigned(10,4); num2 <= to_unsigned(6,4); --more input combinations can be given here. wait; end process stimulus; end;

**Simulation Waveform:**

**Simulation Waveform:**

The codes were simulated in Modelsim. This is a screenshot of the waveform.

__RTL Schematic:__

__RTL Schematic:__

**Note**:- Use RTL Viewer to get a closer look on how your design is actually implemented in hardware.

could you please tell me the types of adders ...

ReplyDeletei know

carry save adder

carry ripple adder

carry look ahead adder

if any adder besides this .....and also which one is best while we code it in vhdl.....and why..??

asmita

hello could you please provide me with the block diagram you used for this coding of carry ripple adder...

ReplyDeletethanks in advance

regards

asmita

@asmi : Ripple adder gives the worst performance, but it is to implement. So if speed is important I suggest go for carry save or carry look ahead adder. Carry save adder is relatively easy to implement. See this:

ReplyDeletehttp://www.ece.tamu.edu/~sshakkot/courses/ecen248/csa-notes.pdf

Some more adders are:

1)Kogge-Stone adder(the fastest adder)

2)Carry bypass adder.

It is difficult to see which adder is the most useful.One way to find out is implementing all of them.

This is the block diagram I used to code the ripple carry adder here:

http://en.labs.wikimedia.org/wiki/File:4-bit_ripple_carry_adder.svg

hello can you please give me vhdl codes for kogge stone adder

ReplyDeletecan any one post carry save adder carry select adder?

ReplyDeletecan anybody gve me the vhdl code for carry save adder

ReplyDeletei have to impement diff adders and multipliers .plse help me

ReplyDelete@vipin : thanxx ....

ReplyDeletecan you help me with verilog coding for 54 bit input using carry propagate adder

ReplyDeleteplease tell me about the architecture or logic diagram of carry save adder.

ReplyDeletecan any body provide me the vhdl code for carry select adder

ReplyDeletecan u help me to write the code in vhdl ..4 bits alu (4 logical ) nd (8 arithematices) operation

ReplyDeletecan u help me by providing vhdl coding for carry select adder?

ReplyDeleteCan u help me to write code for 32bit unsigned multiplier using carry look ahead adder (vhdl code)

ReplyDelete