Writing a Gate Level VHDL design (and Testbench) from Scratch

    In this video I want to show you how you can take a logic circuit diagram and write the corresponding VHDL code along with its testbench. 

The VHDL codes presented in the video are given below:

xor_gate.vhd:

library ieee;
use ieee.std_logic_1164.all;

entity xor_gate is
    port (
        A,B : in std_logic;
        C : out std_logic
    );
end entity;


architecture gate_level of xor_gate is

signal An,Bn,t1,t2 : std_logic := '0';

begin

An <= not A;
Bn <= not B;
t1 <= An and B;
t2 <= Bn and A;

C <= t1 or t2;

end architecture;

tb_xor.vhd:

library ieee;
use ieee.std_logic_1164.all;

entity tb_xor is
end entity;

architecture behav of tb_xor is

component xor_gate is
    port (
        A,B : in std_logic;
        C : out std_logic
    );
end component;

signal A,B,C : std_logic := '0';

begin

UUT : xor_gate port map (A,B,C);

stimulus : process
begin
    A <= '0';
    B <= '0';
    wait for 100 ns;
    A <= '0';
    B <= '1';
    wait for 100 ns;
    A <= '1';
    B <= '0';
    wait for 100 ns;
    A <= '1';
    B <= '1';
    wait;
end process;    

end architecture;

The Logic circuit diagram is given below:

Simulation Waveform from Modelsim: