VHDL code for Hexadecimal to 7-Segment Display Converter

Few years back, I wrote a post on BCD to 7-segment display converter. This code is an update to the old code. The main changes are:

• Removed the clock which was unnecessary.
• Removed the libraries which weren't used.
• Extended for accepting hexadecimal inputs, and not only BCD.

The module takes 4 bit BCD as input and outputs 7 bit decoded output for driving the seven segment display unit. A seven segment display can be used to display hexadecimal digits. They have LED or LCD elements which becomes active when the input is zero.The figure shows how different digits are displayed:

VHDL code for the 7 segment converter:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity to_7seg is
    Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);
          seg7 : out  STD_LOGIC_VECTOR (6 downto 0)
             );
end to_7seg;

architecture Behavioral of to_7seg is

begin

--'a' corresponds to MSB of seg7 and 'g' corresponds to LSB of seg7.
process (A)
BEGIN
    case A is
        when "0000"=> seg7 <="0000001";  -- '0'
        when "0001"=> seg7 <="1001111";  -- '1'
        when "0010"=> seg7 <="0010010";  -- '2'
        when "0011"=> seg7 <="0000110";  -- '3'
        when "0100"=> seg7 <="1001100";  -- '4' 
        when "0101"=> seg7 <="0100100";  -- '5'
        when "0110"=> seg7 <="0100000";  -- '6'
        when "0111"=> seg7 <="0001111";  -- '7'
        when "1000"=> seg7 <="0000000";  -- '8'
        when "1001"=> seg7 <="0000100";  -- '9'
        when "1010"=> seg7 <="0001000";  -- 'A'
        when "1011"=> seg7 <="1100000";  -- 'b'
        when "1100"=> seg7 <="0110001";  -- 'C'
        when "1101"=> seg7 <="1000010";  -- 'd'
        when "1110"=> seg7 <="0110000";  -- 'E'
        when "1111"=> seg7 <="0111000";  -- 'F'
        when others =>  NULL;
    end case;
end process;

end Behavioral;

Testbench code for the converter:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
 
ENTITY tb_seg IS
END tb_seg;
 
ARCHITECTURE behavior OF tb_seg IS 

    COMPONENT to_7seg
    PORT(
         A : IN  std_logic_vector(3 downto 0);
         seg7 : OUT  std_logic_vector(6 downto 0)
        );
    END COMPONENT;
   
   signal A : std_logic_vector(3 downto 0) := (others => '0');
   signal seg7 : std_logic_vector(6 downto 0);
 
BEGIN
 
    -- Instantiate the Unit Under Test (UUT)
   uut: to_7seg PORT MAP (
          A => A,
          seg7 => seg7
        );

  -- Stimulus process
   stim_proc: process
   begin        
        for i in 0 to 15 loop
            A <= conv_std_logic_vector(i,4);
            wait for 50 ns;
        end loop;
      wait;
   end process;

END;

Simulation waveform:

The code was synthesised and simulated using Xilinx ISE 14.6. The following waveform verifies the correct working of the code.

VHDL: BCD to 7-segment display converter

THIS BLOG POST WAS UPDATED ON 4th Mar 2024!

    7-segment displays are commonly used in FPGA (Field-Programmable Gate Array) boards for displaying numeric and sometimes alphanumeric information. These displays consist of seven individual LED segments arranged in a pattern that can display numerals from 0 to 9, as well as some letters such as A-F for hexadecimal displays. 

    To show a certain character using the 7 segment display, you need to lit up the corresponding segments. This is done by not passing a voltage to it, basically driving it with a '0' signal in VHDL.    

The following image shows how the numbers from 0 to 9 can be displayed using a 7 segment display.

 

The following VHDL code can be used to convert bcd digits into 7 bit std_logic_vector signals which can be used to show the correct digits on the display piece. Note that, a in the above picture corresponds to MSB of segment7 and g corresponds to LSB of segment7.

VHDL Entity:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity seven_segment_decoder is
port (
    bcd : in unsigned(3 downto 0);  --BCD input
    -- 'a' corresponds to MSB of segment7 and g corresponds to LSB of segment7.
    segment7 : out std_logic_vector(6 downto 0)  -- 7 bit decoded output.
);
end seven_segment_decoder;

architecture Behavioral of seven_segment_decoder is

begin

process (bcd)
BEGIN
case bcd is
    when "0000"=> segment7 <="0000001";  -- '0'
    when "0001"=> segment7 <="1001111";  -- '1'
    when "0010"=> segment7 <="0010010";  -- '2'
    when "0011"=> segment7 <="0000110";  -- '3'
    when "0100"=> segment7 <="1001100";  -- '4'
    when "0101"=> segment7 <="0100100";  -- '5'
    when "0110"=> segment7 <="0100000";  -- '6'
    when "0111"=> segment7 <="0001111";  -- '7'
    when "1000"=> segment7 <="0000000";  -- '8'
    when "1001"=> segment7 <="0000100";  -- '9'
    --nothing is displayed when a number more than 9 is given as input.
    when others=> segment7 <="1111111";
end case;
end process;

end Behavioral;

    If you want a decimal number of higher than 9 to be displayed using this code, then convert the decimal number into BCD and then instantiate this module for each digit in the BCD code.

Testbench:

Here is a sample test bench code for this module:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

ENTITY tb_seg7_decoder IS
END tb_seg7_decoder;

ARCHITECTURE behavior OF tb_seg7_decoder IS

signal bcd : unsigned(3 downto 0) := (others => '0');
signal segment7 : std_logic_vector(6 downto 0);

BEGIN

--entity port mapping. Usiong 
uut: entity work.seven_segment_decoder PORT MAP 
    (bcd => bcd,
    segment7 => segment7); 

stim_proc: process
begin      
    -- apply an input bcd digit and wait for 100 ns
    -- so that we can check the output in the waveform.         
    for i in 0 to 9 loop
        bcd <= to_unsigned(i,4);
	wait for 100 ns;
    end loop;
end process;

END;

Simulation waveform:

The codes were simulated using modelsim and the following simulation waveform was obtained.