Writing a Gate Level VHDL design (and Testbench) from Scratch

    In this video I want to show you how you can take a logic circuit diagram and write the corresponding VHDL code along with its testbench. 

The VHDL codes presented in the video are given below:

xor_gate.vhd:

library ieee;
use ieee.std_logic_1164.all;

entity xor_gate is
    port (
        A,B : in std_logic;
        C : out std_logic
    );
end entity;


architecture gate_level of xor_gate is

signal An,Bn,t1,t2 : std_logic := '0';

begin

An <= not A;
Bn <= not B;
t1 <= An and B;
t2 <= Bn and A;

C <= t1 or t2;

end architecture;

tb_xor.vhd:

library ieee;
use ieee.std_logic_1164.all;

entity tb_xor is
end entity;

architecture behav of tb_xor is

component xor_gate is
    port (
        A,B : in std_logic;
        C : out std_logic
    );
end component;

signal A,B,C : std_logic := '0';

begin

UUT : xor_gate port map (A,B,C);

stimulus : process
begin
    A <= '0';
    B <= '0';
    wait for 100 ns;
    A <= '0';
    B <= '1';
    wait for 100 ns;
    A <= '1';
    B <= '0';
    wait for 100 ns;
    A <= '1';
    B <= '1';
    wait;
end process;    

end architecture;

The Logic circuit diagram is given below:

Simulation Waveform from Modelsim:

Online Automatic Testbench Generator For VHDL and Simulation Using Xilinx Vivado

Hello guys, I am back here with another video.

If you are someone like me, who suddenly started using the Xilinx Vivado tool after using Xilinx ISE for a long time, then you might have noticed that Vivado currently doesn't support the Automatic testbench generation. 

This is such a major disappointment for many of us. But luckily there are many online tools which does more or less the same. In this Video, I used the Doulos tool for creating testbenches for my VHDL designs. Once generated I tested the codes using the latest Vivado 2019.2 version. 

Hope this is useful for you. Enjoy!

Vivado 2019.2 Beginners Video on how to Create a New Project and Simulate your Design

This is a simple How-To video for Xilinx Vivado 2019.2 version. If you have been already using software tool then you may not need to watch this video.

Previously I had done the same for Xilinx ISE version 14.6. You can check that out here.

In this video, I am trying to show you:

1. How to create a new project.
2. Add VHDL codes to it.
3. Compile and simulate the codes.
4. Verify the code is working, after analyzing the waveform.

Video tutorial on how to simulate a VHDL code using Xilinx ISE

This is the first video, in a series of video tutorials I am planning upload.

In this video, I want to show you

1. how to create a new project.
2. Add VHDL codes to it.
3. Compile and simulate the codes.
4. How to see internal signals in the waveform window.

I have used Xilinx ISE version 14.6 for this demo. The steps should be almost same in other Xilinx versions too.