Online Automatic Testbench Generator For VHDL and Simulation Using Xilinx Vivado

Hello guys, I am back here with another video.

If you are someone like me, who suddenly started using the Xilinx Vivado tool after using Xilinx ISE for a long time, then you might have noticed that Vivado currently doesn't support the Automatic testbench generation. 

This is such a major disappointment for many of us. But luckily there are many online tools which does more or less the same. In this Video, I used the Doulos tool for creating testbenches for my VHDL designs. Once generated I tested the codes using the latest Vivado 2019.2 version. 

Hope this is useful for you. Enjoy!

Vivado 2019.2 Beginners Video on how to Create a New Project and Simulate your Design

This is a simple How-To video for Xilinx Vivado 2019.2 version. If you have been already using software tool then you may not need to watch this video.

Previously I had done the same for Xilinx ISE version 14.6. You can check that out here.

In this video, I am trying to show you:

1. How to create a new project.
2. Add VHDL codes to it.
3. Compile and simulate the codes.
4. Verify the code is working, after analyzing the waveform.